From patchwork Wed Sep 11 13:51:45 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marc Zyngier X-Patchwork-Id: 13800641 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id EC897EE49B3 for ; Wed, 11 Sep 2024 14:15:47 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: MIME-Version:References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From: Reply-To:Content-Type:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=387Xjepx+2QcQwtPMXT2Hu+4k0kBInH3rhTHUfxYYR0=; b=Kvcy4vstX24QIw3J+VrI3eWAKa 4aF1je82zOPRT/seWJBHi5bgIiPaBKRPZbIKoFO/P8E15Bb6f82XFqnebOxI4yAVkPirvffd7aoU2 h56cTSxv9eI/krI5Gt2A8eiEYVtK2MEw+URzFDG10HkixPVoBiVr4vy5//4XYxMDw3OwlDgvxsfG1 UT4QelIo0cA+c+NOgUTOsXp5uaqvj3P3WqanpgJYT4XVXEJZ8H+GUQmxcTJ+qXdO7Vahe53F6fUMW WQYU/K/asJ/F7PAKlvy61oyCKoa/2dx2Y1Dz0ULTPAwjSwVOfmMgOlIX7d+Y21eoz6mdRutVtWJGH jt6Ipd5Q==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1soO87-00000009rbo-0dZH; Wed, 11 Sep 2024 14:15:35 +0000 Received: from dfw.source.kernel.org ([2604:1380:4641:c500::1]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1soNlM-00000009mQb-32oH for linux-arm-kernel@lists.infradead.org; Wed, 11 Sep 2024 13:52:10 +0000 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by dfw.source.kernel.org (Postfix) with ESMTP id 4A93B5C0764; Wed, 11 Sep 2024 13:51:58 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id A3B9DC4CECF; Wed, 11 Sep 2024 13:52:01 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1726062721; bh=pmwfChbV6Lk9uRWDNjOArB44u9RsGn+hZnYvHtlohs0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=HDVI9/0fFUlWhiNHxd603vdghIKHBBpNT/hMQjTP0FA+ahXRGrkxDw/Lxtxw2RlEt EbuMM+9rH9tRbJZy51h9CuycncCmDkZfRv2UFu+O4ni4NmNZHoPIYGyhGxgxmiiKUV /aGc6zHn+jic7DqJvU1ZbZEB7rH/dd05VcibguBxd2RZfRHNEbOGP9OZAIuQmpnlIK HtBqLc8mhBYxWskGaHQ4ato0mmQpwLXc7peK46qvqeXEN7Y1PJbPpjQs5wmMbcxcXv nFystaMyjA7BkXYGwUhX3K47gR2sXFQBGiuNvsQ1UqcrMQQCRw5XObpZ9rJinEmnjp mIGfitWXdZi4w== Received: from sofa.misterjones.org ([185.219.108.64] helo=valley-girl.lan) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.95) (envelope-from ) id 1soNlH-00C7tL-VX; Wed, 11 Sep 2024 14:52:00 +0100 From: Marc Zyngier To: kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org Cc: James Morse , Suzuki K Poulose , Oliver Upton , Zenghui Yu , Joey Gouly , Alexandru Elisei , Mark Brown Subject: [PATCH v3 18/24] KVM: arm64: Split S1 permission evaluation into direct and hierarchical parts Date: Wed, 11 Sep 2024 14:51:45 +0100 Message-Id: <20240911135151.401193-19-maz@kernel.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240911135151.401193-1-maz@kernel.org> References: <20240911135151.401193-1-maz@kernel.org> MIME-Version: 1.0 X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org, james.morse@arm.com, suzuki.poulose@arm.com, oliver.upton@linux.dev, yuzenghui@huawei.com, joey.gouly@arm.com, alexandru.elisei@arm.com, broonie@kernel.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240911_065205_058835_58FD3C8D X-CRM114-Status: GOOD ( 18.24 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The AArch64.S1DirectBasePermissions() pseudocode deals with both direct and hierarchical S1 permission evaluation. While this is probably convenient in the pseudocode, we would like a bit more flexibility to slot things like indirect permissions. To that effect, split the two permission check parts out of handle_at_slow() and into their own functions. The permissions are passed around in a new s1_perms type that contains the individual permissions across the flow. Signed-off-by: Marc Zyngier --- arch/arm64/kvm/at.c | 164 ++++++++++++++++++++++++++------------------ 1 file changed, 99 insertions(+), 65 deletions(-) diff --git a/arch/arm64/kvm/at.c b/arch/arm64/kvm/at.c index 73b2ee662f371..d6ee3a5c30bc2 100644 --- a/arch/arm64/kvm/at.c +++ b/arch/arm64/kvm/at.c @@ -47,6 +47,10 @@ struct s1_walk_result { bool failed; }; +struct s1_perms { + bool ur, uw, ux, pr, pw, px; +}; + static void fail_s1_walk(struct s1_walk_result *wr, u8 fst, bool ptw, bool s2) { wr->fst = fst; @@ -764,111 +768,141 @@ static bool pan3_enabled(struct kvm_vcpu *vcpu, enum trans_regime regime) return sctlr & SCTLR_EL1_EPAN; } -static u64 handle_at_slow(struct kvm_vcpu *vcpu, u32 op, u64 vaddr) +static void compute_s1_direct_permissions(struct kvm_vcpu *vcpu, + struct s1_walk_info *wi, + struct s1_walk_result *wr, + struct s1_perms *s1p) { - bool perm_fail, ur, uw, ux, pr, pw, px; - struct s1_walk_result wr = {}; - struct s1_walk_info wi = {}; - int ret, idx; - - ret = setup_s1_walk(vcpu, op, &wi, &wr, vaddr); - if (ret) - goto compute_par; - - if (wr.level == S1_MMU_DISABLED) - goto compute_par; - - idx = srcu_read_lock(&vcpu->kvm->srcu); - - ret = walk_s1(vcpu, &wi, &wr, vaddr); - - srcu_read_unlock(&vcpu->kvm->srcu, idx); - - if (ret) - goto compute_par; - - /* FIXME: revisit when adding indirect permission support */ - /* AArch64.S1DirectBasePermissions() */ - if (wi.regime != TR_EL2) { - switch (FIELD_GET(PTE_USER | PTE_RDONLY, wr.desc)) { + /* Non-hierarchical part of AArch64.S1DirectBasePermissions() */ + if (wi->regime != TR_EL2) { + switch (FIELD_GET(PTE_USER | PTE_RDONLY, wr->desc)) { case 0b00: - pr = pw = true; - ur = uw = false; + s1p->pr = s1p->pw = true; + s1p->ur = s1p->uw = false; break; case 0b01: - pr = pw = ur = uw = true; + s1p->pr = s1p->pw = s1p->ur = s1p->uw = true; break; case 0b10: - pr = true; - pw = ur = uw = false; + s1p->pr = true; + s1p->pw = s1p->ur = s1p->uw = false; break; case 0b11: - pr = ur = true; - pw = uw = false; + s1p->pr = s1p->ur = true; + s1p->pw = s1p->uw = false; break; } - switch (wr.APTable) { + /* We don't use px for anything yet, but hey... */ + s1p->px = !((wr->desc & PTE_PXN) || s1p->uw); + s1p->ux = !(wr->desc & PTE_UXN); + } else { + s1p->ur = s1p->uw = s1p->ux = false; + + if (!(wr->desc & PTE_RDONLY)) { + s1p->pr = s1p->pw = true; + } else { + s1p->pr = true; + s1p->pw = false; + } + + /* XN maps to UXN */ + s1p->px = !(wr->desc & PTE_UXN); + } +} + +static void compute_s1_hierarchical_permissions(struct kvm_vcpu *vcpu, + struct s1_walk_info *wi, + struct s1_walk_result *wr, + struct s1_perms *s1p) +{ + /* Hierarchical part of AArch64.S1DirectBasePermissions() */ + if (wi->regime != TR_EL2) { + switch (wr->APTable) { case 0b00: break; case 0b01: - ur = uw = false; + s1p->ur = s1p->uw = false; break; case 0b10: - pw = uw = false; + s1p->pw = s1p->uw = false; break; case 0b11: - pw = ur = uw = false; + s1p->pw = s1p->ur = s1p->uw = false; break; } - /* We don't use px for anything yet, but hey... */ - px = !((wr.desc & PTE_PXN) || wr.PXNTable || uw); - ux = !((wr.desc & PTE_UXN) || wr.UXNTable); - - if (op == OP_AT_S1E1RP || op == OP_AT_S1E1WP) { - bool pan; - - pan = *vcpu_cpsr(vcpu) & PSR_PAN_BIT; - pan &= ur || uw || (pan3_enabled(vcpu, wi.regime) && ux); - pw &= !pan; - pr &= !pan; - } + s1p->px &= !wr->PXNTable; + s1p->ux &= !wr->UXNTable; } else { - ur = uw = ux = false; + if (wr->APTable & BIT(1)) + s1p->pw = false; - if (!(wr.desc & PTE_RDONLY)) { - pr = pw = true; - } else { - pr = true; - pw = false; - } + /* XN maps to UXN */ + s1p->px &= !wr->UXNTable; + } +} - if (wr.APTable & BIT(1)) - pw = false; +static void compute_s1_permissions(struct kvm_vcpu *vcpu, u32 op, + struct s1_walk_info *wi, + struct s1_walk_result *wr, + struct s1_perms *s1p) +{ + compute_s1_direct_permissions(vcpu, wi, wr, s1p); + compute_s1_hierarchical_permissions(vcpu, wi, wr, s1p); - /* XN maps to UXN */ - px = !((wr.desc & PTE_UXN) || wr.UXNTable); + if (op == OP_AT_S1E1RP || op == OP_AT_S1E1WP) { + bool pan; + + pan = *vcpu_cpsr(vcpu) & PSR_PAN_BIT; + pan &= s1p->ur || s1p->uw || (pan3_enabled(vcpu, wi->regime) && s1p->ux); + s1p->pw &= !pan; + s1p->pr &= !pan; } +} + +static u64 handle_at_slow(struct kvm_vcpu *vcpu, u32 op, u64 vaddr) +{ + struct s1_walk_result wr = {}; + struct s1_walk_info wi = {}; + struct s1_perms s1p = {}; + bool perm_fail = false; + int ret, idx; + + ret = setup_s1_walk(vcpu, op, &wi, &wr, vaddr); + if (ret) + goto compute_par; + + if (wr.level == S1_MMU_DISABLED) + goto compute_par; + + idx = srcu_read_lock(&vcpu->kvm->srcu); + + ret = walk_s1(vcpu, &wi, &wr, vaddr); + + srcu_read_unlock(&vcpu->kvm->srcu, idx); + + if (ret) + goto compute_par; - perm_fail = false; + compute_s1_permissions(vcpu, op, &wi, &wr, &s1p); switch (op) { case OP_AT_S1E1RP: case OP_AT_S1E1R: case OP_AT_S1E2R: - perm_fail = !pr; + perm_fail = !s1p.pr; break; case OP_AT_S1E1WP: case OP_AT_S1E1W: case OP_AT_S1E2W: - perm_fail = !pw; + perm_fail = !s1p.pw; break; case OP_AT_S1E0R: - perm_fail = !ur; + perm_fail = !s1p.ur; break; case OP_AT_S1E0W: - perm_fail = !uw; + perm_fail = !s1p.uw; break; case OP_AT_S1E1A: case OP_AT_S1E2A: