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Wed, 18 Sep 2024 15:00:00 -0700 From: Besar Wicaksono To: , , , , CC: , , , , , , , , "Besar Wicaksono" Subject: [PATCH 3/3] perf: arm_cspmu: nvidia: enable NVLINK-C2C port filtering Date: Wed, 18 Sep 2024 21:58:46 +0000 Message-ID: <20240918215846.1424282-4-bwicaksono@nvidia.com> X-Mailer: git-send-email 2.46.1 In-Reply-To: <20240918215846.1424282-1-bwicaksono@nvidia.com> References: <20240918215846.1424282-1-bwicaksono@nvidia.com> MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH3PEPF00000009:EE_|CH3PR12MB7762:EE_ X-MS-Office365-Filtering-Correlation-Id: 1d112fcf-c67c-4593-f781-08dcd82d43ae X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|1800799024|36860700013|376014; X-Microsoft-Antispam-Message-Info: zgQ+WSy9lBRNDZ7vTWBr8oPlLNSF/1Kti24rCGumtwRbCMy3bRtWIOG66SJwyTQ2mihavv9Zso7pyEZkykEKB2YYdDy8DYIJo4kqpkSQ7o6/rWcyRJy+EtPrskRI7fp6uI4enizJYCrru3EP/nCVO2214yQ7y2gkw0/jBWMdeW2BH+lqcJRhzz1UOsQ8HRu/RYITquVTLe9rzYPb7+FxbqKjEX7yS2+n6zWSk7F/wDMtIlMzOiag3TK8M3uEcqNomzQQeBMktcRI9asoDDqdNPa3K2KwXzdma3q7r71/pzFGioraBodWurngxrUcXznR+chap0LRK7E1V2BO/QqDNxyc/P8FmCuNF9ldfGEv8o7Y3Gdjc5hZyp4dvPijTBrjVDg3O567I4d8JexeyAqF/MImyEiusfJlwn2GlHvC1kRG0/ofJYpm/o6gEXCzbfBD+zEyqhTDUKcvugBxcu31czVhdlwWO8M2C9b9HVkfhv1CQc4YnoHpClp6VaGIucJMq/IqS5nGh2rmui/eVVWZ/Egqv8MTbgiDXy3i9UkVEkL34VTsblozFoAcATipoYBI4C87vvHqWXDQKKRw1IEZrPqpZIawMlGnFx3Li7rVJgw6RORZoYQYYxsHyWKT5qInNcEwU67T/gZwLkTAxmb+61K5XkPa2eUyB7V5wGiE+iRt7J8nZNXyo2M2p3Psh2ZxEdJJMEabCZBTqP4Y2cj0MXbHcPuS1lwHM3FKpLcav9N2e/EPFrnbella2W0nCAy7GOg19UjoDW05iArLGa+9ffp/tMWAyF1TyUdVNTf0xE1jMtvKbsZWg2NYlMNA0Qe6Nekiy3InAJcc5kkYQ0pcSvbXKgZ9U7uOBlZTPZ9hqFOv6TruTIQHe8xWaen1Ll5UC/qBecN83ntetIlSkv9S2pHYLrTDFnNhT5ygHWdtskq6WixLL4JTOR2lgRICv+kWdv9jDtqeyC70uJUG71uWKjPNl/Hz9AsWhckBjl8fnWGGSMRPUE5HPAzLvlV8P5ygggURyNR2BiDdSzVNEdh7uNp4fTikkxlCdcSbJ54M+JwU8GCnBpskngVr0MfcFNNHaFspqi+g+CucrRxVYoGj/uhS/CFIH0PyEdFccXy5m5ApxdgrFrXTe2HVhm42V3h7xLwEKL+uwLTnzcgxAdkxctpxS3tyXJOadNgGO5L/0/5kfAtUbkCO/oP1eQiWiSTIkF68wdp0RzE4tlWDkeNmPnD1d+N3GQFLpe4qi8KoZc6KdI4P2Ixh9Ktjv1MwQxOKflDZkFrEVJ2sF5UQUvFV8A1wB0SC3oXaIg2qwkgFPev30MbTN1Em3oBbWTXHsPEYCOHLt6W1mJ0iNysApMO0tUpbxH2r+SeT3dIqp/Fk3+QN7/BO9cVzSSgsu4iyEDsnqYNC7u6EKHLml98Qggj9JCCs9g3cB4wQsCAx8dtla9XwfwhDrN3c+RW3vTHn7Ig8 X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230040)(82310400026)(1800799024)(36860700013)(376014);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Sep 2024 22:00:09.8873 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 1d112fcf-c67c-4593-f781-08dcd82d43ae X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH3PEPF00000009.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB7762 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240918_150019_381261_E153977D X-CRM114-Status: GOOD ( 14.27 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Enable NVLINK-C2C port filtering to distinguish traffic from different GPUs connected to NVLINK-C2C. Signed-off-by: Besar Wicaksono --- Documentation/admin-guide/perf/nvidia-pmu.rst | 32 +++++++++++++++++++ drivers/perf/arm_cspmu/nvidia_cspmu.c | 7 ++-- 2 files changed, 36 insertions(+), 3 deletions(-) diff --git a/Documentation/admin-guide/perf/nvidia-pmu.rst b/Documentation/admin-guide/perf/nvidia-pmu.rst index 2e0d47cfe7ea..6d1d3206b4ad 100644 --- a/Documentation/admin-guide/perf/nvidia-pmu.rst +++ b/Documentation/admin-guide/perf/nvidia-pmu.rst @@ -86,6 +86,22 @@ Example usage: perf stat -a -e nvidia_nvlink_c2c0_pmu_3/event=0x0/ +The NVLink-C2C has two ports that can be connected to one GPU (occupying both +ports) or to two GPUs (one GPU per port). The user can use "port" bitmap +parameter to select the port(s) to monitor. Each bit represents the port number, +e.g. "port=0x1" corresponds to port 0 and "port=0x3" is for port 0 and 1. The +PMU will monitor both ports by default if not specified. + +Example for port filtering: + +* Count event id 0x0 from the GPU connected with socket 0 on port 0:: + + perf stat -a -e nvidia_nvlink_c2c0_pmu_0/event=0x0,port=0x1/ + +* Count event id 0x0 from the GPUs connected with socket 0 on port 0 and port 1:: + + perf stat -a -e nvidia_nvlink_c2c0_pmu_0/event=0x0,port=0x3/ + NVLink-C2C1 PMU ------------------- @@ -116,6 +132,22 @@ Example usage: perf stat -a -e nvidia_nvlink_c2c1_pmu_3/event=0x0/ +The NVLink-C2C has two ports that can be connected to one GPU (occupying both +ports) or to two GPUs (one GPU per port). The user can use "port" bitmap +parameter to select the port(s) to monitor. Each bit represents the port number, +e.g. "port=0x1" corresponds to port 0 and "port=0x3" is for port 0 and 1. The +PMU will monitor both ports by default if not specified. + +Example for port filtering: + +* Count event id 0x0 from the GPU connected with socket 0 on port 0:: + + perf stat -a -e nvidia_nvlink_c2c1_pmu_0/event=0x0,port=0x1/ + +* Count event id 0x0 from the GPUs connected with socket 0 on port 0 and port 1:: + + perf stat -a -e nvidia_nvlink_c2c1_pmu_0/event=0x0,port=0x3/ + CNVLink PMU --------------- diff --git a/drivers/perf/arm_cspmu/nvidia_cspmu.c b/drivers/perf/arm_cspmu/nvidia_cspmu.c index d1cd9975e71a..cd51177347e5 100644 --- a/drivers/perf/arm_cspmu/nvidia_cspmu.c +++ b/drivers/perf/arm_cspmu/nvidia_cspmu.c @@ -149,6 +149,7 @@ static struct attribute *pcie_pmu_format_attrs[] = { static struct attribute *nvlink_c2c_pmu_format_attrs[] = { ARM_CSPMU_FORMAT_EVENT_ATTR, + ARM_CSPMU_FORMAT_ATTR(port, "config1:0-1"), NULL, }; @@ -193,7 +194,7 @@ static u32 nv_cspmu_event_filter(const struct perf_event *event) const struct nv_cspmu_ctx *ctx = to_nv_cspmu_ctx(to_arm_cspmu(event->pmu)); - if (ctx->filter_mask == 0) + if (ctx->filter_mask == 0 || event->attr.config1 == 0) return ctx->filter_default_val; return event->attr.config1 & ctx->filter_mask; @@ -229,7 +230,7 @@ static const struct nv_cspmu_match nv_cspmu_match[] = { { .prodid = 0x104, .prodid_mask = NV_PRODID_MASK, - .filter_mask = 0x0, + .filter_mask = NV_NVL_C2C_FILTER_ID_MASK, .filter_default_val = NV_NVL_C2C_FILTER_ID_MASK, .name_pattern = "nvidia_nvlink_c2c1_pmu_%u", .name_fmt = NAME_FMT_SOCKET, @@ -239,7 +240,7 @@ static const struct nv_cspmu_match nv_cspmu_match[] = { { .prodid = 0x105, .prodid_mask = NV_PRODID_MASK, - .filter_mask = 0x0, + .filter_mask = NV_NVL_C2C_FILTER_ID_MASK, .filter_default_val = NV_NVL_C2C_FILTER_ID_MASK, .name_pattern = "nvidia_nvlink_c2c0_pmu_%u", .name_fmt = NAME_FMT_SOCKET,