From patchwork Thu Sep 19 13:47:23 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Andrei Stefanescu X-Patchwork-Id: 13807777 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 8E43ACF3942 for ; Thu, 19 Sep 2024 13:53:49 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:MIME-Version: Content-Transfer-Encoding:Content-Type:References:In-Reply-To:Message-ID:Date :Subject:Cc:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=MQi7i+4aEouje7mWUyll8Elatm3DJMHU6rtOOmUPpnU=; b=HOg1ST5Vpg4tpwc9vpJyo4Hhxo eUQUZLwjcF44y3qWav5cg/R1PseWyCp0Thls8j/APo2kX2nNntdQTScn1ML4rjl+7ieDOvFEt2+Bn JqlqTa1uzcaeTETJNArmF5PEya0K/X67pGgdX4mxVhtAGo+iELIBRd+KKxQth+pulnLeNa7gZRyql b3kxCE+WNDUi656BwhXHNtEpYUR/D1M/H+1sYJhfJ+CRyGvp+gE+pJ0F8vCGDfyLOHE8xU67Gu+xy dVNftEgphnVuJn41myDI00v6cE89ifwbTbgS+I1CJmXkLO+EWijQxxYiWOWsyhT6tvh4rZqk6a3zO ty8omUzg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1srHbF-0000000ANsj-1a38; Thu, 19 Sep 2024 13:53:37 +0000 Received: from mail-westeuropeazlp170100000.outbound.protection.outlook.com ([2a01:111:f403:c201::] helo=AM0PR83CU005.outbound.protection.outlook.com) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1srHWt-0000000AN8m-3bGL for linux-arm-kernel@lists.infradead.org; Thu, 19 Sep 2024 13:49:09 +0000 ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=pwm/jql5QADeHVEBipTQzh1cVg1waQS9ZnvlczvAgJhP8XV05zl3/EX7JMz4fwmitfPMiYtW/aLbJWVTbAYfmuxq8FE5JdZ7bDGBfOE177uMkM35L4zGdZ4mVasDAC0Ollawn3iOtWegnrdelFIFEVF1DB5LaGue5boFqWcGVXxce3vSSoBe4a4hZ7eB37Q89E4/qaKpG50E5ewgyYUaevGPa2sRtuinR1LInSdG9qd8aj3QkPWugzaoWpfn2jwvCmbJuh8Bhddvm3gAQl0SUz0oMIyBMj3rcYScukvE8FPC/6PgMyE9Q5yz2p7Tr/Eo/vCMJq+5svh4bDDfR9FOtg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=MQi7i+4aEouje7mWUyll8Elatm3DJMHU6rtOOmUPpnU=; b=u4zT7az/mJk/Axp8/+NQrlCsDq4Zaoh/WMl8feS0uuJ5kudSch56LbV56jZyNaxhZE+CvyAt7NeqMNxsCz59dJDMhc/lREDRG6lMbkdsbMztGXWvstxW/YV4XgdEfKBWLmgir4MnstSw4mgx926PORBGknaYBhg3qpBJf6IiY0id7ziN/taQQyfzmgqqpHTchaA0J/wQgJOP7aLhptE7YRbgTn3VF51qQ2ElMoq2x1N8tG8kHU/rko9aAyCmsUBrusnwThA/oMemVeiYizlnJE9Z/MdFyrUikQfx0LeESXQlssa0vf9Z24O39LSbUy6vQBX5VeI63+jjGPIaLVhknw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=oss.nxp.com; dmarc=pass action=none header.from=oss.nxp.com; dkim=pass header.d=oss.nxp.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=NXP1.onmicrosoft.com; s=selector1-NXP1-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=MQi7i+4aEouje7mWUyll8Elatm3DJMHU6rtOOmUPpnU=; b=rXUvkjc2aL/jvx8Mlk769IjpwW0KGd+ay65JMpBkJG5HFrUF5/llMPt5eYxusivzpIq1XiNKdL4zhDnzQCE/C8HwiZ4YbQS/s1fb5bo64UJH4JaqKOLKdjDwgPC1gmy9o6Ra4Dx2p+/6Zoit7besN7RUeccUAaN1IEQ39EFXelGG0GuIY/nvgsu3HQkTH9TEoWjuN9enDNbN7X+KXzYmhnOT8erAU709/YhsZrncKrs4Daah7XHqCZPVtiuPsNNaS+YqKSGjB6L+iMTRiiHTMQgIcEmpmUccT1YwaGF63ko5hoqF3ETzNB/XCMAATvXUjP65ofaRALFwWGeQhSQO6Q== Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=oss.nxp.com; Received: from AM9PR04MB8487.eurprd04.prod.outlook.com (2603:10a6:20b:41a::6) by VI2PR04MB10267.eurprd04.prod.outlook.com (2603:10a6:800:225::7) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7962.24; Thu, 19 Sep 2024 13:48:54 +0000 Received: from AM9PR04MB8487.eurprd04.prod.outlook.com ([fe80::6d7a:8d2:f020:455]) by AM9PR04MB8487.eurprd04.prod.outlook.com ([fe80::6d7a:8d2:f020:455%5]) with mapi id 15.20.7962.022; Thu, 19 Sep 2024 13:48:54 +0000 From: Andrei Stefanescu To: Linus Walleij , Bartosz Golaszewski , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chester Lin , Matthias Brugger , Greg Kroah-Hartman , "Rafael J. Wysocki" Cc: linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, NXP S32 Linux Team , Andrei Stefanescu Subject: [PATCH v3 3/4] gpio: siul2-s32g2: add NXP S32G2/S32G3 SoCs support Date: Thu, 19 Sep 2024 16:47:23 +0300 Message-ID: <20240919134732.2626144-4-andrei.stefanescu@oss.nxp.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240919134732.2626144-1-andrei.stefanescu@oss.nxp.com> References: <20240919134732.2626144-1-andrei.stefanescu@oss.nxp.com> X-ClientProxiedBy: AM0PR10CA0109.EURPRD10.PROD.OUTLOOK.COM (2603:10a6:208:e6::26) To AM9PR04MB8487.eurprd04.prod.outlook.com (2603:10a6:20b:41a::6) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: AM9PR04MB8487:EE_|VI2PR04MB10267:EE_ X-MS-Office365-Filtering-Correlation-Id: d49c1b87-c674-419b-183e-08dcd8b1cd21 X-MS-Exchange-SharedMailbox-RoutingAgent-Processed: True X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|366016|376014|7416014|52116014|38350700014; X-Microsoft-Antispam-Message-Info: =?utf-8?q?kCWe0kPPX/jnJifMF6HenMw3Af6Tusd?= =?utf-8?q?0Hoxip6lAjIg6kUZVtvSIpdLmH5rj29ayC1hU6G1ssgIu/Zs7XFDpNeGK2QtoBKXw?= =?utf-8?q?cfI2W0GDG/BuEskjfwRFbldjNzpBepfuz5FalaAmEVxBABfUkWZsNV2wjaccmVzpK?= =?utf-8?q?7RgDcEON3oNcMZGWBlBbwxryeJQj59UULgHspAlHfWEu8D4sP3MQjh46TBybXC6aT?= =?utf-8?q?aBYgqVUppizmrGvg6PtYkqn61w7oAJ8v/OJsJKt+GoKZKXJjL38dXJNePFXLzz/7u?= =?utf-8?q?N6tTJM4HZr1OzB1L/Xv2tMninHvhC8kCb1+g9aOpR9EFNc4Dw7aZ20m5eac2JJ0vq?= =?utf-8?q?VJuy8t4yOP5Yd02XnT5dzfvsLqChpoNKT7XjU+7fk8zuZ03olgXt0Anl9AjLHmkxJ?= =?utf-8?q?ASKmSBKbmtUpMvPW1Enm5Apf/xAKbburZiqOZZ1bJh4+vfAhHpGwIsJkzGBaVjBjg?= =?utf-8?q?E5p/jnolh15fakplxECzDcGoJS0B931tpQeLKA61mratoqX5PZ7IE1sAEa4o8j8Ly?= =?utf-8?q?bmZkG8VcArZ/LEJnsNYhq49Y1C94rCOLbydaAmbkgdoBgPUOtsljDc/Wd+WSFglTN?= =?utf-8?q?4ikCIjEhJLU/LyJ4CBQpk4X20Y1b3XLlXVwpckwTMBZZYdDgWTOLpMy0c4Jrwsa2t?= =?utf-8?q?XYvqB2ti04GF3q6LgLp0PuKzN1J1IKmiNZf0tiFWmD7vNN0z24fwBQoXpmpkD0tSD?= =?utf-8?q?KWYtVn/InQ/ljYLCGDlpJ1iWwz2JKOVskiDLbyFdQF0oraeLefjY/Yh3lDVTxdMqI?= =?utf-8?q?P8NT9G3RPW8zNsL45xpvcSM3dIqbbpV85u6LtFYnFfd1UWzHpjwOy654fT9MBwSPs?= =?utf-8?q?0le5DLqhBSqwrK5/dO9wxW1KICVnI7l5BE/jU091q8iXAoNaEBl8wf7cNBTyiJYww?= =?utf-8?q?7N6hFTjVIdQ28nN2sBim7PXxJgaxD6ArtIOLh14wtuMsmWf2aYiNVu4om9HUZxYBi?= =?utf-8?q?qvJ9eFIjQ7oLS+g6g8p2nO8M52Hc1dHPcW0nzjygWGjC1pjjCXd+FpNPOud9UiAzg?= =?utf-8?q?Ovz+eurwlwygZV6bv5oBNAt1rkvhdorLUS5qviH65qOrjex+p3SUL9N0qQHi4Q2bS?= =?utf-8?q?zw1PYxhIrrbDW18xYhPV9D/0PbophUU8E9HX3vOhN8EhS1Q8sMH15J9ztkERx/d3h?= =?utf-8?q?3tdhXHTYSS1rQPv+MLrhJG7VVU36hXd/MXTJl3mq97Z6RB0S7X2SiAGA/ZsiI7tLN?= =?utf-8?q?cxIaDJBv0fl7wugfoG6eBuBB4iuNzTVqsDMRvDIBqmGEsj74VBXuAGX7pTKsK8k4C?= =?utf-8?q?52fQ+lTBklHxjyrH0m/Iu2Lg3h1ZRfJusA7f+cS9KA22tayQ24LNUpmb0ke4TEscp?= =?utf-8?q?XTgKdtWC8K5NcOfPfQqo2KCb4mnL+UQ4DQ=3D=3D?= X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:AM9PR04MB8487.eurprd04.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230040)(1800799024)(366016)(376014)(7416014)(52116014)(38350700014);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?utf-8?q?q8n24dS8lLuVIKKy46DxZuFB9Ie/?= =?utf-8?q?UJTLD6MYsKEK5Wj4IhM4zivSNtVlaoK2AEadXEhLjr4OQAHC2MIh7PQsFh3KFqzXg?= =?utf-8?q?dRvu2LgFIKHjHPDBWr6MZIhKKXD678+st3FhqLABNevqJZIE3yMLSB0jnV9jn5wq7?= =?utf-8?q?mP4h2rPQxEFY3H/Larx+xyhJ7O3zfd6E1prLuIu0iopxmmE2GoqkYt/bMxdVRhVc/?= =?utf-8?q?FCJM79/rK10nIlhoRXdEb5Qrdw+xZ3DVrNs2sVVkpSfauBREFOk4zNGRIYu6zJjRS?= =?utf-8?q?Ao5YJ1Jzsnq0WzYXjBqKJZmfm4wUTic7kKTEyIpHPsSzQoLPpeyLVs8TeqtnqqVRb?= =?utf-8?q?Gbqm1/2Lkj7pQA+s0RGZebnyN/AelnmRqpZ/l7ix3L/I6+ec9adg3e9aap9NbwSLc?= =?utf-8?q?VlDhAo0pxskvwviUmLsn5i8GoeJ3PlwxxsG+MyE4iiV1llyWwJGzjooHCDKGbAVlN?= =?utf-8?q?QEDBskOnjUPWiIUo5nPmXGHqOhP7vuzgylRfTLAPY8DSLj9bGK4fD4HdKgGolUeap?= =?utf-8?q?VVAtRuvFfIJX8D1NhwiNiVqUAGEZXKchwJgaE/4Jehxv82OHew2ZkL6zBw6pKkWpe?= =?utf-8?q?/+v88aJvLUNQLatHU25sTon/iKBvgTo5pdRKUq5OrFihcdgXFWs8Pe4WJRaiYZoEu?= =?utf-8?q?gZDFo5oDDsF+XKb3zBp+AjL72xpzwl/+i4Kl4qKbyib3mXmMIZUj1kh+ow8J9txk/?= =?utf-8?q?kNjqEehKcA1Ko52OvvVtGdH9LYhG34B+o8fgPBWAuS8FXUDV7chailAQUl9enOxYT?= =?utf-8?q?6SKVIFqfZnKEVI0PpVt2ijytfjwPCE8L6dDDZsZ/eKnaPQEl4zhCEs4odIJ2RLsG/?= =?utf-8?q?BFNLV3xYv9jUzUZH3tGzYxy7eS/NVipPOq0u1vwHYWcByFi3s2+NDlCQAEGxVZRLE?= =?utf-8?q?u+yZsLNcJUiQKaaTiicx1TXg+pjXnhaqsu8jYSy8RtrjwbVJIhepPN4wPKS0t7FYP?= =?utf-8?q?2IC2nrNPYRLYmacgf6g5OpJlU5g3b1SLN2OWnXZuS0uaU2R3LLyKkOTlih6bC9/NM?= =?utf-8?q?s/sT1mrDAxFf4yA1XVEE0Jw9/huJ+8FLEbkYwlbCeEhOUyWQmnpU8mFhMAGA7heRX?= =?utf-8?q?IuAhGStkP3vSVE10AYLB7D12ffDW6dzBMxwT3CC7uW18nF+NLEV3NRaEhNs9azUuh?= =?utf-8?q?Mi2zkBR1XjfjvPIimAfMRTBsv2ZqKGYv4IRBbuc4CHj/sG0+vdroWH4AvBvHq5CEm?= =?utf-8?q?ft33WITSjo1pRVdfCXMf+N5KvPWihPw9OdYtZv6erb6Qotsw0S0YU43BKn615svlE?= =?utf-8?q?a1FRvvEZMZD8dKMRDKpBfkWlOt0kT24JcgqdaLq3fo93ca49+iuCyM/lTLrjH2cRU?= =?utf-8?q?rICtdyIKH8xX7kDePNwgMro/uPA7tqdG8Cm0BUHPSLE1uINHzOsfJ3hOZQ29BrJ58?= =?utf-8?q?KtC88+Y8sZRAZecDgQQp5U07hZ5LlNBUBxISkCr/KxChcfc+0ehq/P3aCqKq9pOhV?= =?utf-8?q?N1IrnY9bewnlvp3LHDKi1QRqQR+X0M3pgQiL8j4gM42Cea2pgULk1CruNHMUCwu5Q?= =?utf-8?q?dL+r61p/F1IoHIFIsaxa4Ppe0g5HDle44w=3D=3D?= X-OriginatorOrg: oss.nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: d49c1b87-c674-419b-183e-08dcd8b1cd21 X-MS-Exchange-CrossTenant-AuthSource: AM9PR04MB8487.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Sep 2024 13:48:54.3706 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: bxIzTghbWeyFM9cQPchyU66HWdhqCOuUOlBIYwXP1WoLs9MV9t5laZ9cp+DK+NtZvs469alT8pEy2RmB3j7Hgbzio/jcdnEsQ8ruIZiTPs8= X-MS-Exchange-Transport-CrossTenantHeadersStamped: VI2PR04MB10267 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240919_064907_995407_B5F7DBE2 X-CRM114-Status: GOOD ( 22.42 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add the GPIO driver for S32G2/S32G3 SoCs. This driver uses the SIUL2 (System Integration Unit Lite2) hardware module. There are two SIUL2 hardware modules present, SIUL2_0(controlling GPIOs 0-101) and SIUL2_1 for the rest. The GPIOs are not fully contiguous, there are some gaps: - GPIO102 up to GPIO111(inclusive) are invalid - GPIO123 up to GPIO143(inclusive) are invalid Some GPIOs are input only(i.e. GPI182) though this restriction is not yet enforced in code. This patch adds basic GPIO functionality(no interrupts, no suspend/resume functions). Signed-off-by: Ghennadi Procopciuc Signed-off-by: Larisa Grigore Signed-off-by: Phu Luu An Signed-off-by: Andrei Stefanescu --- drivers/gpio/Kconfig | 10 + drivers/gpio/Makefile | 1 + drivers/gpio/gpio-siul2-s32g2.c | 576 ++++++++++++++++++++++++++++++++ 3 files changed, 587 insertions(+) create mode 100644 drivers/gpio/gpio-siul2-s32g2.c diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index 58f43bcced7c..75a6ca60ebc7 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -643,6 +643,16 @@ config GPIO_SIOX Say yes here to support SIOX I/O devices. These are units connected via a SIOX bus and have a number of fixed-direction I/O lines. +config GPIO_SIUL2_S32G2 + tristate "GPIO driver for S32G2/S32G3" + depends on ARCH_S32 || COMPILE_TEST + depends on OF_GPIO + select REGMAP_MMIO + help + This enables support for the SIUL2 GPIOs found on the S32G2/S32G3 + chips. Say yes here to enable the SIUL2 to be used as an GPIO + controller for S32G2/S32G3 platforms. + config GPIO_SNPS_CREG bool "Synopsys GPIO via CREG (Control REGisters) driver" depends on ARC || COMPILE_TEST diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index 64dd6d9d730d..fb6e770a64b9 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -149,6 +149,7 @@ obj-$(CONFIG_GPIO_SCH) += gpio-sch.o obj-$(CONFIG_GPIO_SIFIVE) += gpio-sifive.o obj-$(CONFIG_GPIO_SIM) += gpio-sim.o obj-$(CONFIG_GPIO_SIOX) += gpio-siox.o +obj-$(CONFIG_GPIO_SIUL2_S32G2) += gpio-siul2-s32g2.o obj-$(CONFIG_GPIO_SL28CPLD) += gpio-sl28cpld.o obj-$(CONFIG_GPIO_SLOPPY_LOGIC_ANALYZER) += gpio-sloppy-logic-analyzer.o obj-$(CONFIG_GPIO_SODAVILLE) += gpio-sodaville.o diff --git a/drivers/gpio/gpio-siul2-s32g2.c b/drivers/gpio/gpio-siul2-s32g2.c new file mode 100644 index 000000000000..a69cbb3bcfaf --- /dev/null +++ b/drivers/gpio/gpio-siul2-s32g2.c @@ -0,0 +1,576 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * SIUL2 GPIO support. + * + * Copyright (c) 2016 Freescale Semiconductor, Inc. + * Copyright 2018-2024 NXP + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* PGPDOs are 16bit registers that come in big endian + * order if they are grouped in pairs of two. + * + * For example, the order is PGPDO1, PGPDO0, PGPDO3, PGPDO2... + */ +#define SIUL2_PGPDO(N) (((N) ^ 1) * 2) +#define S32G2_SIUL2_NUM 2 +#define S32G2_PADS_DTS_TAG_LEN (7) + +#define SIUL2_GPIO_16_PAD_SIZE 16 + +/** + * struct siul2_device_data - platform data attached to the compatible. + * @pad_access: access table for I/O pads, consists of S32G2_SIUL2_NUM tables. + * @reset_cnt: reset the pin name counter to zero when switching to SIUL2_1. + */ +struct siul2_device_data { + const struct regmap_access_table **pad_access; + const bool reset_cnt; +}; + +/** + * struct siul2_desc - describes a SIUL2 hw module. + * @pad_access: array of valid I/O pads. + * @opadmap: the regmap of the Parallel GPIO Pad Data Out Register. + * @ipadmap: the regmap of the Parallel GPIO Pad Data In Register. + * @gpio_base: the first GPIO pin. + * @gpio_num: the number of GPIO pins. + */ +struct siul2_desc { + const struct regmap_access_table *pad_access; + struct regmap *opadmap; + struct regmap *ipadmap; + u32 gpio_base; + u32 gpio_num; +}; + +/** + * struct siul2_gpio_dev - describes a group of GPIO pins. + * @platdata: the platform data. + * @siul2: SIUL2_0 and SIUL2_1 modules information. + * @pin_dir_bitmap: the bitmap with pin directions. + * @gc: the GPIO chip. + * @lock: mutual access to bitmaps. + */ +struct siul2_gpio_dev { + const struct siul2_device_data *platdata; + struct siul2_desc siul2[S32G2_SIUL2_NUM]; + unsigned long *pin_dir_bitmap; + struct gpio_chip gc; + raw_spinlock_t lock; +}; + +static const struct regmap_range s32g2_siul20_pad_yes_ranges[] = { + regmap_reg_range(SIUL2_PGPDO(0), SIUL2_PGPDO(0)), + regmap_reg_range(SIUL2_PGPDO(1), SIUL2_PGPDO(1)), + regmap_reg_range(SIUL2_PGPDO(2), SIUL2_PGPDO(2)), + regmap_reg_range(SIUL2_PGPDO(3), SIUL2_PGPDO(3)), + regmap_reg_range(SIUL2_PGPDO(4), SIUL2_PGPDO(4)), + regmap_reg_range(SIUL2_PGPDO(5), SIUL2_PGPDO(5)), + regmap_reg_range(SIUL2_PGPDO(6), SIUL2_PGPDO(6)), +}; + +static const struct regmap_access_table s32g2_siul20_pad_access_table = { + .yes_ranges = s32g2_siul20_pad_yes_ranges, + .n_yes_ranges = ARRAY_SIZE(s32g2_siul20_pad_yes_ranges), +}; + +static const struct regmap_range s32g2_siul21_pad_yes_ranges[] = { + regmap_reg_range(SIUL2_PGPDO(7), SIUL2_PGPDO(7)), + regmap_reg_range(SIUL2_PGPDO(9), SIUL2_PGPDO(9)), + regmap_reg_range(SIUL2_PGPDO(10), SIUL2_PGPDO(10)), + regmap_reg_range(SIUL2_PGPDO(11), SIUL2_PGPDO(11)), +}; + +static const struct regmap_access_table s32g2_siul21_pad_access_table = { + .yes_ranges = s32g2_siul21_pad_yes_ranges, + .n_yes_ranges = ARRAY_SIZE(s32g2_siul21_pad_yes_ranges), +}; + +static const struct regmap_access_table *s32g2_pad_access_table[] = { + &s32g2_siul20_pad_access_table, + &s32g2_siul21_pad_access_table +}; + +static_assert(ARRAY_SIZE(s32g2_pad_access_table) == S32G2_SIUL2_NUM); + +static const struct siul2_device_data s32g2_device_data = { + .pad_access = s32g2_pad_access_table, + .reset_cnt = true, +}; + +static int siul2_get_gpio_pinspec(struct platform_device *pdev, + struct of_phandle_args *pinspec, + unsigned int range_index) +{ + struct device_node *np = pdev->dev.of_node; + + return of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, + range_index, pinspec); +} + +static struct regmap *siul2_offset_to_regmap(struct siul2_gpio_dev *dev, + unsigned int offset, + bool input) +{ + struct siul2_desc *siul2; + size_t i; + + for (i = 0; i < ARRAY_SIZE(dev->siul2); i++) { + siul2 = &dev->siul2[i]; + if (offset >= siul2->gpio_base && + offset - siul2->gpio_base < siul2->gpio_num) + return input ? siul2->ipadmap : siul2->opadmap; + } + + return NULL; +} + +static void siul2_gpio_set_direction(struct siul2_gpio_dev *dev, + unsigned int gpio, int dir) +{ + guard(raw_spinlock_irqsave)(&dev->lock); + + if (dir == GPIO_LINE_DIRECTION_IN) + __clear_bit(gpio, dev->pin_dir_bitmap); + else + __set_bit(gpio, dev->pin_dir_bitmap); +} + +static int siul2_get_direction(struct siul2_gpio_dev *dev, + unsigned int gpio) +{ + return test_bit(gpio, dev->pin_dir_bitmap) ? GPIO_LINE_DIRECTION_OUT : + GPIO_LINE_DIRECTION_IN; +} + +static struct siul2_gpio_dev *to_siul2_gpio_dev(struct gpio_chip *chip) +{ + return container_of(chip, struct siul2_gpio_dev, gc); +} + +static int siul2_gpio_dir_in(struct gpio_chip *chip, unsigned int gpio) +{ + struct siul2_gpio_dev *gpio_dev; + int ret = 0; + + ret = pinctrl_gpio_direction_input(chip, gpio); + if (ret) + return ret; + + gpio_dev = to_siul2_gpio_dev(chip); + siul2_gpio_set_direction(gpio_dev, gpio, GPIO_LINE_DIRECTION_IN); + + return 0; +} + +static int siul2_gpio_get_dir(struct gpio_chip *chip, unsigned int gpio) +{ + return siul2_get_direction(to_siul2_gpio_dev(chip), gpio); +} + +static unsigned int siul2_pin2pad(unsigned int pin) +{ + return pin / SIUL2_GPIO_16_PAD_SIZE; +} + +static u16 siul2_pin2mask(unsigned int pin) +{ + /** + * From Reference manual : + * PGPDOx[PPDOy] = GPDO(x × 16) + (15 - y)[PDO_(x × 16) + (15 - y)] + */ + return BIT(SIUL2_GPIO_16_PAD_SIZE - 1 - pin % SIUL2_GPIO_16_PAD_SIZE); +} + +static void siul2_gpio_set_val(struct gpio_chip *chip, unsigned int offset, + int value) +{ + struct siul2_gpio_dev *gpio_dev = to_siul2_gpio_dev(chip); + unsigned int pad, reg_offset; + struct regmap *regmap; + u16 mask; + + mask = siul2_pin2mask(offset); + pad = siul2_pin2pad(offset); + + reg_offset = SIUL2_PGPDO(pad); + regmap = siul2_offset_to_regmap(gpio_dev, offset, false); + if (!regmap) + return; + + value = value ? mask : 0; + + regmap_update_bits(regmap, reg_offset, mask, value); +} + +static int siul2_gpio_dir_out(struct gpio_chip *chip, unsigned int gpio, + int val) +{ + struct siul2_gpio_dev *gpio_dev; + int ret = 0; + + gpio_dev = to_siul2_gpio_dev(chip); + siul2_gpio_set_val(chip, gpio, val); + + ret = pinctrl_gpio_direction_output(chip, gpio); + if (ret) + return ret; + + siul2_gpio_set_direction(gpio_dev, gpio, GPIO_LINE_DIRECTION_OUT); + + return 0; +} + +static void siul2_gpio_set(struct gpio_chip *chip, unsigned int offset, + int value) +{ + struct siul2_gpio_dev *gpio_dev = to_siul2_gpio_dev(chip); + + if (!gpio_dev) + return; + + if (siul2_get_direction(gpio_dev, offset) == GPIO_LINE_DIRECTION_IN) + return; + + siul2_gpio_set_val(chip, offset, value); +} + +static int siul2_gpio_get(struct gpio_chip *chip, unsigned int offset) +{ + struct siul2_gpio_dev *gpio_dev = to_siul2_gpio_dev(chip); + unsigned int mask, pad, reg_offset, data = 0; + struct regmap *regmap; + + mask = siul2_pin2mask(offset); + pad = siul2_pin2pad(offset); + + reg_offset = SIUL2_PGPDO(pad); + regmap = siul2_offset_to_regmap(gpio_dev, offset, true); + if (!regmap) + return -EINVAL; + + regmap_read(regmap, reg_offset, &data); + + return !!(data & mask); +} + +static const struct regmap_config siul2_regmap_conf = { + .val_bits = 32, + .reg_bits = 32, + .reg_stride = 4, + .cache_type = REGCACHE_FLAT, +}; + +static struct regmap *common_regmap_init(struct platform_device *pdev, + struct regmap_config *conf, + const char *name) +{ + struct device *dev = &pdev->dev; + struct resource *res; + resource_size_t size; + void __iomem *base; + + base = devm_platform_get_and_ioremap_resource_byname(pdev, name, &res); + if (IS_ERR(base)) { + dev_err(&pdev->dev, "Failed to get MEM resource: %s\n", name); + return ERR_PTR(-EINVAL); + } + + size = resource_size(res); + conf->val_bits = conf->reg_stride * 8; + conf->max_register = size - conf->reg_stride; + conf->name = name; + conf->use_raw_spinlock = true; + + if (conf->cache_type != REGCACHE_NONE) + conf->num_reg_defaults_raw = size / conf->reg_stride; + + return devm_regmap_init_mmio(dev, base, conf); +} + +static bool not_writable(__always_unused struct device *dev, + __always_unused unsigned int reg) +{ + return false; +} + +static struct regmap *init_padregmap(struct platform_device *pdev, + struct siul2_gpio_dev *gpio_dev, + int selector, bool input) +{ + const struct siul2_device_data *platdata = gpio_dev->platdata; + struct regmap_config regmap_conf = siul2_regmap_conf; + char dts_tag[S32G2_PADS_DTS_TAG_LEN]; + int err; + + regmap_conf.reg_stride = 2; + + if (selector != 0 && selector != 1) + return ERR_PTR(-EINVAL); + + regmap_conf.rd_table = platdata->pad_access[selector]; + + err = snprintf(dts_tag, ARRAY_SIZE(dts_tag), "%cpads%d", + input ? 'i' : 'o', selector); + if (err < 0) + return ERR_PTR(-EINVAL); + + if (input) { + regmap_conf.writeable_reg = not_writable; + regmap_conf.cache_type = REGCACHE_NONE; + } else { + regmap_conf.wr_table = platdata->pad_access[selector]; + } + + return common_regmap_init(pdev, ®map_conf, dts_tag); +} + +static int siul2_gpio_pads_init(struct platform_device *pdev, + struct siul2_gpio_dev *gpio_dev) +{ + struct device *dev = &pdev->dev; + size_t i; + + for (i = 0; i < ARRAY_SIZE(gpio_dev->siul2); i++) { + gpio_dev->siul2[i].opadmap = init_padregmap(pdev, gpio_dev, i, + false); + if (IS_ERR(gpio_dev->siul2[i].opadmap)) { + dev_err(dev, + "Failed to initialize opad2%zu regmap config\n", + i); + return PTR_ERR(gpio_dev->siul2[i].opadmap); + } + + gpio_dev->siul2[i].ipadmap = init_padregmap(pdev, gpio_dev, i, + true); + if (IS_ERR(gpio_dev->siul2[i].ipadmap)) { + dev_err(dev, + "Failed to initialize ipad2%zu regmap config\n", + i); + return PTR_ERR(gpio_dev->siul2[i].ipadmap); + } + } + + return 0; +} + +static int siul2_gen_names(struct device *dev, unsigned int cnt, char **names, + char *ch_index, unsigned int *num_index) +{ + unsigned int i; + + for (i = 0; i < cnt; i++) { + if (i != 0 && !(*num_index % 16)) + (*ch_index)++; + + names[i] = devm_kasprintf(dev, GFP_KERNEL, "P%c_%02d", + *ch_index, 0xFU & (*num_index)++); + if (!names[i]) + return -ENOMEM; + } + + return 0; +} + +static int siul2_gpio_remove_reserved_names(struct device *dev, + struct siul2_gpio_dev *gpio_dev, + char **names) +{ + struct device_node *np = dev->of_node; + int num_ranges, i, j, ret; + u32 base_gpio, num_gpio; + + /* Parse the gpio-reserved-ranges to know which GPIOs to exclude. */ + + num_ranges = of_property_count_u32_elems(dev->of_node, + "gpio-reserved-ranges"); + + /* The "gpio-reserved-ranges" is optional. */ + if (num_ranges < 0) + return 0; + num_ranges /= 2; + + for (i = 0; i < num_ranges; i++) { + ret = of_property_read_u32_index(np, "gpio-reserved-ranges", + i * 2, &base_gpio); + if (ret) { + dev_err(dev, "Could not parse the start GPIO: %d\n", + ret); + return ret; + } + + ret = of_property_read_u32_index(np, "gpio-reserved-ranges", + i * 2 + 1, &num_gpio); + if (ret) { + dev_err(dev, "Could not parse num. GPIOs: %d\n", ret); + return ret; + } + + if (base_gpio + num_gpio > gpio_dev->gc.ngpio) { + dev_err(dev, "Reserved GPIOs outside of GPIO range\n"); + return -EINVAL; + } + + /* Remove names set for reserved GPIOs. */ + for (j = base_gpio; j < base_gpio + num_gpio; j++) { + devm_kfree(dev, names[j]); + names[j] = NULL; + } + } + + return 0; +} + +static int siul2_gpio_populate_names(struct device *dev, + struct siul2_gpio_dev *gpio_dev) +{ + unsigned int num_index = 0; + char ch_index = 'A'; + char **names; + int i, ret; + + names = devm_kcalloc(dev, gpio_dev->gc.ngpio, sizeof(*names), + GFP_KERNEL); + if (!names) + return -ENOMEM; + + for (i = 0; i < S32G2_SIUL2_NUM; i++) { + ret = siul2_gen_names(dev, gpio_dev->siul2[i].gpio_num, + names + gpio_dev->siul2[i].gpio_base, + &ch_index, &num_index); + if (ret) { + dev_err(dev, "Could not set names for SIUL2_%d GPIOs\n", + i); + return ret; + } + + if (gpio_dev->platdata->reset_cnt) + num_index = 0; + + ch_index++; + } + + ret = siul2_gpio_remove_reserved_names(dev, gpio_dev, names); + if (ret) + return ret; + + gpio_dev->gc.names = (const char *const *)names; + + return 0; +} + +static int siul2_gpio_probe(struct platform_device *pdev) +{ + struct siul2_gpio_dev *gpio_dev; + struct device *dev = &pdev->dev; + struct of_phandle_args pinspec; + size_t i, bitmap_size; + struct gpio_chip *gc; + int ret = 0; + + gpio_dev = devm_kzalloc(dev, sizeof(*gpio_dev), GFP_KERNEL); + if (!gpio_dev) + return -ENOMEM; + + gpio_dev->platdata = &s32g2_device_data; + + for (i = 0; i < S32G2_SIUL2_NUM; i++) + gpio_dev->siul2[i].pad_access = + gpio_dev->platdata->pad_access[i]; + + ret = siul2_gpio_pads_init(pdev, gpio_dev); + if (ret) + return ret; + + gc = &gpio_dev->gc; + + platform_set_drvdata(pdev, gpio_dev); + + raw_spin_lock_init(&gpio_dev->lock); + + for (i = 0; i < ARRAY_SIZE(gpio_dev->siul2); i++) { + ret = siul2_get_gpio_pinspec(pdev, &pinspec, i); + if (ret) { + dev_err(dev, + "unable to get pinspec %zu from device tree\n", + i); + return -EINVAL; + } + + of_node_put(pinspec.np); + + if (pinspec.args_count != 3) { + dev_err(dev, "Invalid pinspec count: %d\n", + pinspec.args_count); + return -EINVAL; + } + + gpio_dev->siul2[i].gpio_base = pinspec.args[1]; + gpio_dev->siul2[i].gpio_num = pinspec.args[2]; + } + + gc->base = -1; + + /* In some cases, there is a gap between the SIUL GPIOs. */ + gc->ngpio = gpio_dev->siul2[S32G2_SIUL2_NUM - 1].gpio_base + + gpio_dev->siul2[S32G2_SIUL2_NUM - 1].gpio_num; + + ret = siul2_gpio_populate_names(&pdev->dev, gpio_dev); + if (ret) + return ret; + + bitmap_size = BITS_TO_LONGS(gc->ngpio) * + sizeof(*gpio_dev->pin_dir_bitmap); + gpio_dev->pin_dir_bitmap = devm_kzalloc(dev, bitmap_size, GFP_KERNEL); + if (!gpio_dev->pin_dir_bitmap) + return -ENOMEM; + + gc->parent = dev; + gc->label = dev_name(dev); + + gc->set = siul2_gpio_set; + gc->get = siul2_gpio_get; + gc->set_config = gpiochip_generic_config; + gc->request = gpiochip_generic_request; + gc->free = gpiochip_generic_free; + gc->direction_output = siul2_gpio_dir_out; + gc->direction_input = siul2_gpio_dir_in; + gc->get_direction = siul2_gpio_get_dir; + gc->owner = THIS_MODULE; + + ret = devm_gpiochip_add_data(dev, gc, gpio_dev); + if (ret) + return dev_err_probe(dev, ret, "unable to add gpiochip\n"); + + return 0; +} + +static const struct of_device_id siul2_gpio_dt_ids[] = { + { .compatible = "nxp,s32g2-siul2-gpio" }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, siul2_gpio_dt_ids); + +static struct platform_driver siul2_gpio_driver = { + .driver = { + .name = "s32g2-siul2-gpio", + .of_match_table = siul2_gpio_dt_ids, + }, + .probe = siul2_gpio_probe, +}; + +module_platform_driver(siul2_gpio_driver); + +MODULE_AUTHOR("NXP"); +MODULE_DESCRIPTION("NXP SIUL2 GPIO"); +MODULE_LICENSE("GPL");