From patchwork Mon Sep 23 10:06:11 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Billy Tsai X-Patchwork-Id: 13809491 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 86A28CF9C6F for ; Mon, 23 Sep 2024 10:15:26 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Type: Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date :Subject:To:From:Reply-To:Cc:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=h74t+0dkWF74sy82G+FzhqDM2sz+ZOL1/s76GaYoYp8=; b=psXI/1o3im7pBu8lJxewKvsRl7 xwIBcRqId0rDdaTD20bLhx5KDSc0UNbeN0IG0tAbMlxURUKFgejdK1zIYSkA4MWzRiPPAZSUVoipy cIB/1xEFDeOW8jwMzj8bubVYaaHqmQN7qJU8dvnmh1C6LXpc76bvWvdeiJDOE2HqmOwQEfTxaXfyH 8jUnuvSWxSft35IpQTZebNww51iqfhvAZg/7UUJMMYHqJK9sYj5bc/WF6ltqlggJBPWJvv/UHgyjK Bieht7htDq2QSks6K5JhFcMqWede1DjqRy3QbJvErAI0fXl8Y2XKEqyEz1SiJWPj1iSstQyX7wA8V 767DoF+g==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1ssg66-0000000Gwkj-1Zig; Mon, 23 Sep 2024 10:15:14 +0000 Received: from mail.aspeedtech.com ([211.20.114.72] helo=TWMBX01.aspeed.com) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1ssfxc-0000000Gv0C-0CIE for linux-arm-kernel@lists.infradead.org; Mon, 23 Sep 2024 10:06:29 +0000 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.12; Mon, 23 Sep 2024 18:06:12 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1258.12 via Frontend Transport; Mon, 23 Sep 2024 18:06:12 +0800 From: Billy Tsai To: , , , , , , , , , , , , , , Subject: [PATCH v5 6/6] gpio: aspeed: Add the flush write to ensure the write complete. Date: Mon, 23 Sep 2024 18:06:11 +0800 Message-ID: <20240923100611.1597113-7-billy_tsai@aspeedtech.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240923100611.1597113-1-billy_tsai@aspeedtech.com> References: <20240923100611.1597113-1-billy_tsai@aspeedtech.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240923_030628_112082_E4582B65 X-CRM114-Status: GOOD ( 10.03 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Performing a dummy read ensures that the register write operation is fully completed, mitigating any potential bus delays that could otherwise impact the frequency of bitbang usage. E.g., if the JTAG application uses GPIO to control the JTAG pins (TCK, TMS, TDI, TDO, and TRST), and the application sets the TCK clock to 1 MHz, the GPIO's high/low transitions will rely on a delay function to ensure the clock frequency does not exceed 1 MHz. However, this can lead to rapid toggling of the GPIO because the write operation is POSTed and does not wait for a bus acknowledgment. Signed-off-by: Billy Tsai --- drivers/gpio/gpio-aspeed.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpio/gpio-aspeed.c b/drivers/gpio/gpio-aspeed.c index 230af90aa966..e7dcc37e40f9 100644 --- a/drivers/gpio/gpio-aspeed.c +++ b/drivers/gpio/gpio-aspeed.c @@ -402,6 +402,8 @@ static void __aspeed_gpio_set(struct gpio_chip *gc, unsigned int offset, struct aspeed_gpio *gpio = gpiochip_get_data(gc); gpio->config->llops->reg_bit_set(gpio, offset, reg_val, val); + // flush write + gpio->config->llops->reg_bit_get(gpio, offset, reg_val); } static void aspeed_gpio_set(struct gpio_chip *gc, unsigned int offset,