From patchwork Tue Sep 24 09:50:46 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dhruva Gole X-Patchwork-Id: 13810650 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id BA409CF9C74 for ; Tue, 24 Sep 2024 10:03:11 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:CC:To:In-Reply-To:References :Message-ID:Content-Transfer-Encoding:Content-Type:MIME-Version:Subject:Date: From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=QeoCQfMkCQADOer2TgZxIF8m7AprUWBAy1/d+sbV/2M=; b=gfX3lCckxmsOjLTiDoag/SNpi9 AvgIfJXrjBlmNc/cri56NbJD9XgBjQLTaEhfqsrXlO+r6Nyw8BoBa1Cqum8/ENThdRu6pxQk+DQKg PaDX6ElROTXBp2tmdJSNTOY9bq5ILVvIKOtErtGqBJIPqSsuzXwDoiMPBzPkTQbMt/ZqN2wIy4Tbs 6rYJjumUgYLmTGPCkFM0o+3lybNN76TzOOLgsVkve32mHVpaAex2LFeELF5oc8GcIo3oWquNf4x65 2BNfPvHlD2mYK9SsUqDdcH6V7UBlBvWhdzIFCemXWHa1LRvkyVfZzzbAvy+5FmhLmdWcduSYdJaDK /xGq0Jug==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1st2Nn-00000001vGF-2y6t; Tue, 24 Sep 2024 10:02:59 +0000 Received: from fllv0016.ext.ti.com ([198.47.19.142]) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1st2Ch-00000001syy-14uV for linux-arm-kernel@lists.infradead.org; Tue, 24 Sep 2024 09:51:32 +0000 Received: from lelv0265.itg.ti.com ([10.180.67.224]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 48O9pSWc003212; Tue, 24 Sep 2024 04:51:28 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1727171488; bh=QeoCQfMkCQADOer2TgZxIF8m7AprUWBAy1/d+sbV/2M=; h=From:Date:Subject:References:In-Reply-To:To:CC; b=nBaDzqwb6MVxVceHkbjWkP5UHC0KdnRjebzz+6oqFo8MphqBujflDNBSWbV0hBEyd Ngh0sNZ88WZULv0J4/Nmp2/JYL7HTBJlssd276NPFMderqJQPsmtOa1fTi1i4RGxx9 knAhOvcjq3kccujW3mfcGEM7h3MuNxMV1zJ1lfuI= Received: from DFLE100.ent.ti.com (dfle100.ent.ti.com [10.64.6.21]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 48O9pR4b001109 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 24 Sep 2024 04:51:27 -0500 Received: from DFLE105.ent.ti.com (10.64.6.26) by DFLE100.ent.ti.com (10.64.6.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Tue, 24 Sep 2024 04:51:27 -0500 Received: from lelvsmtp6.itg.ti.com (10.180.75.249) by DFLE105.ent.ti.com (10.64.6.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Tue, 24 Sep 2024 04:51:28 -0500 Received: from [127.0.1.1] (lcpd911.dhcp.ti.com [172.24.227.226]) by lelvsmtp6.itg.ti.com (8.15.2/8.15.2) with ESMTP id 48O9owSv017217; Tue, 24 Sep 2024 04:51:23 -0500 From: Dhruva Gole Date: Tue, 24 Sep 2024 15:20:46 +0530 Subject: [PATCH v5 6/6] cpufreq: ti-cpufreq: Update efuse/rev offsets in AM62 family MIME-Version: 1.0 Message-ID: <20240924-ti-cpufreq-fixes-v5-v5-6-cbe16b9ddb1b@ti.com> References: <20240924-ti-cpufreq-fixes-v5-v5-0-cbe16b9ddb1b@ti.com> In-Reply-To: <20240924-ti-cpufreq-fixes-v5-v5-0-cbe16b9ddb1b@ti.com> To: Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley , "Rafael J. Wysocki" , Viresh Kumar CC: , , , , Andrew Davis , Bryan Brattlof , Dhruva Gole X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1727171458; l=1509; i=d-gole@ti.com; s=20240919; h=from:subject:message-id; bh=MdcHjICSpj3jCUd6bD1wEhgq64QDj+cNSJHu45+y/Zc=; b=zrW5/Ctpd0tlw/Wd7DOLEV4OODMMPTYP7G9B1A0wAu8d0i4qc+SLtYRVwEWrFQ1OHfn8pt2Te YGB8tvLZDK7C9ljPQBADMn2Rml3RrsvfUK0b5lEnpTxKzpnhU0iM3Mh X-Developer-Key: i=d-gole@ti.com; a=ed25519; pk=k8NnY4RbxVqeqGsYfTHeVn4hPOHkjg7Mii0Ixs4rghM= X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240924_025131_427669_0BA8C8B9 X-CRM114-Status: GOOD ( 12.75 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org With the Silicon revision being taken directly from socinfo, there's no longer any need for reading any SOC register for revision from this driver. Hence, we do not require any rev_offset for AM62 family of devices. The efuse offset should be 0x0 for AM625 as well, as the syscon register being used from DT refers to the efuse_offset directly. Signed-off-by: Dhruva Gole --- drivers/cpufreq/ti-cpufreq.c | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/drivers/cpufreq/ti-cpufreq.c b/drivers/cpufreq/ti-cpufreq.c index ba621ce1cdda694c98867422dbb7f10c0df2afef..870ab0b376c1c0389b952b61a13d169b174538bb 100644 --- a/drivers/cpufreq/ti-cpufreq.c +++ b/drivers/cpufreq/ti-cpufreq.c @@ -313,10 +313,9 @@ static const struct soc_device_attribute k3_cpufreq_soc[] = { static struct ti_cpufreq_soc_data am625_soc_data = { .efuse_xlate = am625_efuse_xlate, - .efuse_offset = 0x0018, + .efuse_offset = 0x0, .efuse_mask = 0x07c0, .efuse_shift = 0x6, - .rev_offset = 0x0014, .multi_regulator = false, }; @@ -325,7 +324,6 @@ static struct ti_cpufreq_soc_data am62a7_soc_data = { .efuse_offset = 0x0, .efuse_mask = 0x07c0, .efuse_shift = 0x6, - .rev_offset = 0x0014, .multi_regulator = false, }; @@ -334,7 +332,6 @@ static struct ti_cpufreq_soc_data am62p5_soc_data = { .efuse_offset = 0x0, .efuse_mask = 0x07c0, .efuse_shift = 0x6, - .rev_offset = 0x0014, .multi_regulator = false, };