@@ -1744,7 +1744,7 @@ imp_iic_wrap_en: clock-controller@11ec2000 {
};
efuse: efuse@11f20000 {
- compatible = "mediatek,mt8188-efuse", "mediatek,efuse";
+ compatible = "mediatek,mt8188-efuse", "mediatek,mt8186-efuse";
reg = <0 0x11f20000 0 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
@@ -1752,6 +1752,11 @@ efuse: efuse@11f20000 {
lvts_efuse_data1: lvts1-calib@1ac {
reg = <0x1ac 0x40>;
};
+
+ gpu_speedbin: gpu-speedbin@580 {
+ reg = <0x581 0x1>;
+ bits = <0 3>;
+ };
};
gpu: gpu@13000000 {
@@ -1763,6 +1768,8 @@ gpu: gpu@13000000 {
<GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH 0>;
interrupt-names = "job", "mmu", "gpu";
+ nvmem-cells = <&gpu_speedbin>;
+ nvmem-cell-names = "speed-bin";
operating-points-v2 = <&gpu_opp_table>;
power-domains = <&spm MT8188_POWER_DOMAIN_MFG2>,
<&spm MT8188_POWER_DOMAIN_MFG3>,
The OPP table of mt8188 GPU contains duplicated frequencies for different speed bins. In order to support OPP table, we need to provide the speed bin info in the efuse data so the GPU driver could properly set the supported hardware speed bin. Same as mt8186, the efuse data for mt8188's GPU speed binning requires post-process to convert the bit field format expected by the OPP table. Signed-off-by: Pablo Sun <pablo.sun@mediatek.com> --- arch/arm64/boot/dts/mediatek/mt8188.dtsi | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-)