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AJvYcCUCoTxxhcSuMWgnwxJc1/YaV1Rot9649vMphycji+89SCIxKDhL3rltIfeoX9m6490ZPwzCWfrYlPad03hCdYUw@lists.infradead.org X-Gm-Message-State: AOJu0YzFspXjXNvFgd8u4hMVZSIxJanzbFrTSyErphmn4wzbkDLOSLXr ztbQGGtGgVk52XeQMlZF8Dv99fXKD6XseLOPZa7sREhqw5svLcND4yJuCc3Iwg== X-Google-Smtp-Source: AGHT+IF6JPGrnrw2s+oul2cFZeq8gjPoe0hpHOYv+WskSpMyeJxxVC8NL1KQVuNJIk0Wtb2UocnhVQ== X-Received: by 2002:a05:6a00:1254:b0:714:2533:1b82 with SMTP id d2e1a72fcca58-71dc5d6f693mr4955317b3a.23.1727869616721; Wed, 02 Oct 2024 04:46:56 -0700 (PDT) Received: from fshao-p620.tpe.corp.google.com ([2401:fa00:1:10:3bd0:d371:4a25:3576]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-71b2652baefsm9639627b3a.180.2024.10.02.04.46.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 02 Oct 2024 04:46:56 -0700 (PDT) From: Fei Shao To: AngeloGioacchino Del Regno Cc: Fei Shao , Conor Dooley , Krzysztof Kozlowski , Matthias Brugger , Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org Subject: [PATCH 3/9] arm64: dts: mediatek: mt8188: Add MIPI DSI nodes Date: Wed, 2 Oct 2024 19:41:43 +0800 Message-ID: <20241002114614.847553-4-fshao@chromium.org> X-Mailer: git-send-email 2.46.1.824.gd892dcdcdd-goog In-Reply-To: <20241002114614.847553-1-fshao@chromium.org> References: <20241002114614.847553-1-fshao@chromium.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241002_044657_787540_5DD6880A X-CRM114-Status: GOOD ( 11.76 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add MIPI DSI and the associated PHY node to support DSI panels. Individual board device tree should enable the nodes as needed. Signed-off-by: Fei Shao --- arch/arm64/boot/dts/mediatek/mt8188.dtsi | 26 ++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8188.dtsi b/arch/arm64/boot/dts/mediatek/mt8188.dtsi index 9431f3c5c228..ff639418bebe 100644 --- a/arch/arm64/boot/dts/mediatek/mt8188.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8188.dtsi @@ -1837,6 +1837,16 @@ pcieport: pcie-phy@0 { }; }; + mipi_tx_phy: dsi-phy@11c80000 { + compatible = "mediatek,mt8188-mipi-tx", "mediatek,mt8183-mipi-tx"; + reg = <0 0x11c80000 0 0x1000>; + clocks = <&clk26m>; + clock-output-names = "mipi_tx0_pll"; + #clock-cells = <0>; + #phy-cells = <0>; + status = "disabled"; + }; + i2c1: i2c@11e00000 { compatible = "mediatek,mt8188-i2c"; reg = <0 0x11e00000 0 0x1000>, @@ -2222,10 +2232,26 @@ larb19: smi@1a010000 { mediatek,smi = <&vdo_smi_common>; }; + disp_dsi: dsi@1c008000 { + compatible = "mediatek,mt8188-dsi"; + reg = <0 0x1c008000 0 0x1000>; + clocks = <&vdosys0 CLK_VDO0_DSI0>, + <&vdosys0 CLK_VDO0_DSI0_DSI>, + <&mipi_tx_phy>; + clock-names = "engine", "digital", "hs"; + interrupts = ; + phys = <&mipi_tx_phy>; + phy-names = "dphy"; + power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>; + resets = <&vdosys0 MT8188_VDO0_RST_DSI0>; + status = "disabled"; + }; + vdosys0: syscon@1c01d000 { compatible = "mediatek,mt8188-vdosys0", "syscon"; reg = <0 0x1c01d000 0 0x1000>; #clock-cells = <1>; + #reset-cells = <1>; mboxes = <&gce0 0 CMDQ_THR_PRIO_4>; mediatek,gce-client-reg = <&gce0 SUBSYS_1c01XXXX 0xd000 0x1000>; };