diff mbox series

[v2,3/9] arm64: dts: mediatek: mt8188: Add MIPI DSI nodes

Message ID 20241003070139.1461472-4-fshao@chromium.org (mailing list archive)
State New, archived
Headers show
Series Add platform supports to MediaTek MT8188 SoC (part 2) | expand

Commit Message

Fei Shao Oct. 3, 2024, 6:59 a.m. UTC 
Add MIPI DSI and the associated PHY node to support DSI panels.
Individual board device tree should enable the nodes as needed.

Signed-off-by: Fei Shao <fshao@chromium.org>
---

(no changes since v1)

 arch/arm64/boot/dts/mediatek/mt8188.dtsi | 26 ++++++++++++++++++++++++
 1 file changed, 26 insertions(+)

Comments

AngeloGioacchino Del Regno Oct. 3, 2024, 8:36 a.m. UTC | #1 
Il 03/10/24 08:59, Fei Shao ha scritto:
> Add MIPI DSI and the associated PHY node to support DSI panels.
> Individual board device tree should enable the nodes as needed.
> 
> Signed-off-by: Fei Shao <fshao@chromium.org>
> ---
> 
> (no changes since v1)
> 
>   arch/arm64/boot/dts/mediatek/mt8188.dtsi | 26 ++++++++++++++++++++++++
>   1 file changed, 26 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/mediatek/mt8188.dtsi b/arch/arm64/boot/dts/mediatek/mt8188.dtsi
> index 23101d316c4e..719d2409a7db 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8188.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8188.dtsi
> @@ -1839,6 +1839,16 @@ pcieport: pcie-phy@0 {
>   			};
>   		};
>   
> +		mipi_tx_phy: dsi-phy@11c80000 {

There are two DSI PHYs, one at 0x11c80000 and one at 0x11c90000

> +			compatible = "mediatek,mt8188-mipi-tx", "mediatek,mt8183-mipi-tx";
> +			reg = <0 0x11c80000 0 0x1000>;
> +			clocks = <&clk26m>;
> +			clock-output-names = "mipi_tx0_pll";
> +			#clock-cells = <0>;
> +			#phy-cells = <0>;
> +			status = "disabled";
> +		};
> +
>   		i2c1: i2c@11e00000 {
>   			compatible = "mediatek,mt8188-i2c";
>   			reg = <0 0x11e00000 0 0x1000>,
> @@ -2224,10 +2234,26 @@ larb19: smi@1a010000 {
>   			mediatek,smi = <&vdo_smi_common>;
>   		};
>   
> +		disp_dsi: dsi@1c008000 {

And there are two DSIs, one at 0x1c008000 and one at 0x1c012000

Cheers,
Angelo
Fei Shao Oct. 4, 2024, 4:23 a.m. UTC | #2 
On Thu, Oct 3, 2024 at 4:36 PM AngeloGioacchino Del Regno
<angelogioacchino.delregno@collabora.com> wrote:
>
> Il 03/10/24 08:59, Fei Shao ha scritto:
> > Add MIPI DSI and the associated PHY node to support DSI panels.
> > Individual board device tree should enable the nodes as needed.
> >
> > Signed-off-by: Fei Shao <fshao@chromium.org>
> > ---
> >
> > (no changes since v1)
> >
> >   arch/arm64/boot/dts/mediatek/mt8188.dtsi | 26 ++++++++++++++++++++++++
> >   1 file changed, 26 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/mediatek/mt8188.dtsi b/arch/arm64/boot/dts/mediatek/mt8188.dtsi
> > index 23101d316c4e..719d2409a7db 100644
> > --- a/arch/arm64/boot/dts/mediatek/mt8188.dtsi
> > +++ b/arch/arm64/boot/dts/mediatek/mt8188.dtsi
> > @@ -1839,6 +1839,16 @@ pcieport: pcie-phy@0 {
> >                       };
> >               };
> >
> > +             mipi_tx_phy: dsi-phy@11c80000 {
>
> There are two DSI PHYs, one at 0x11c80000 and one at 0x11c90000
>
> > +                     compatible = "mediatek,mt8188-mipi-tx", "mediatek,mt8183-mipi-tx";
> > +                     reg = <0 0x11c80000 0 0x1000>;
> > +                     clocks = <&clk26m>;
> > +                     clock-output-names = "mipi_tx0_pll";
> > +                     #clock-cells = <0>;
> > +                     #phy-cells = <0>;
> > +                     status = "disabled";
> > +             };
> > +
> >               i2c1: i2c@11e00000 {
> >                       compatible = "mediatek,mt8188-i2c";
> >                       reg = <0 0x11e00000 0 0x1000>,
> > @@ -2224,10 +2234,26 @@ larb19: smi@1a010000 {
> >                       mediatek,smi = <&vdo_smi_common>;
> >               };
> >
> > +             disp_dsi: dsi@1c008000 {
>
> And there are two DSIs, one at 0x1c008000 and one at 0x1c012000

Thanks for pointing them out, I'll add them for the second DSI.

Regards,
Fei
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/mediatek/mt8188.dtsi b/arch/arm64/boot/dts/mediatek/mt8188.dtsi
index 23101d316c4e..719d2409a7db 100644
--- a/arch/arm64/boot/dts/mediatek/mt8188.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8188.dtsi
@@ -1839,6 +1839,16 @@  pcieport: pcie-phy@0 {
 			};
 		};
 
+		mipi_tx_phy: dsi-phy@11c80000 {
+			compatible = "mediatek,mt8188-mipi-tx", "mediatek,mt8183-mipi-tx";
+			reg = <0 0x11c80000 0 0x1000>;
+			clocks = <&clk26m>;
+			clock-output-names = "mipi_tx0_pll";
+			#clock-cells = <0>;
+			#phy-cells = <0>;
+			status = "disabled";
+		};
+
 		i2c1: i2c@11e00000 {
 			compatible = "mediatek,mt8188-i2c";
 			reg = <0 0x11e00000 0 0x1000>,
@@ -2224,10 +2234,26 @@  larb19: smi@1a010000 {
 			mediatek,smi = <&vdo_smi_common>;
 		};
 
+		disp_dsi: dsi@1c008000 {
+			compatible = "mediatek,mt8188-dsi";
+			reg = <0 0x1c008000 0 0x1000>;
+			clocks = <&vdosys0 CLK_VDO0_DSI0>,
+				 <&vdosys0 CLK_VDO0_DSI0_DSI>,
+				 <&mipi_tx_phy>;
+			clock-names = "engine", "digital", "hs";
+			interrupts = <GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH 0>;
+			phys = <&mipi_tx_phy>;
+			phy-names = "dphy";
+			power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>;
+			resets = <&vdosys0 MT8188_VDO0_RST_DSI0>;
+			status = "disabled";
+		};
+
 		vdosys0: syscon@1c01d000 {
 			compatible = "mediatek,mt8188-vdosys0", "syscon";
 			reg = <0 0x1c01d000 0 0x1000>;
 			#clock-cells = <1>;
+			#reset-cells = <1>;
 			mboxes = <&gce0 0 CMDQ_THR_PRIO_4>;
 			mediatek,gce-client-reg = <&gce0 SUBSYS_1c01XXXX 0xd000 0x1000>;
 		};