From patchwork Fri Oct 4 13:19:33 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Machon X-Patchwork-Id: 13822361 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4BA77CFA779 for ; Fri, 4 Oct 2024 13:29:35 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:CC:To:In-Reply-To:References :Message-ID:Content-Transfer-Encoding:Content-Type:MIME-Version:Subject:Date: From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=t85w8eF+nxbmHE7Gy0KZg1+yh/RGwk/sZUlgIhk3Lyg=; b=3eHOU6uCmUBSdCJs2ArOGAtoKm 9BQ8WP9LXCCwPuLtKvqavSYzyWzFyFpTY/7M2pA8dmWCamkNGk+tvUpsmQj9Kt8bny9iJ4KlboA8p WBjhUDibmLQioJ0hU6XlQDfZHQ0FtBCCBRuoouYZWn9I1WF2KQ9o2dPp4QXDJYzT4RsGKtAnhSQ6i yN6KSBISrTgkKYmfWb9LHP28NAj6/LC/w1bUS03/z52lX6e//peFbskup8mYU3dbSMVxMpMTsygz4 JBVkzOGc6fxkT54uslk/ugj48q0EetZu3SJGJyjQQ/0zDvc4qgenH0pcuphHOsneo6nqzPHVMpzrp JHi9Kwig==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1swiN1-0000000CX8C-0FaL; Fri, 04 Oct 2024 13:29:23 +0000 Received: from esa.microchip.iphmx.com ([68.232.153.233]) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1swiEY-0000000CUF8-0REf for linux-arm-kernel@lists.infradead.org; Fri, 04 Oct 2024 13:20:40 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1728048037; x=1759584037; h=from:date:subject:mime-version:content-transfer-encoding: message-id:references:in-reply-to:to:cc; bh=KmyIuWKSCAIec9Kz7ykRLXXXQBHQhKcUie7XEf3f4pk=; b=mUnxAzNOVNJE4DcrZA0f85gvQ1oNniPsARq+QtjJIPuT9O5BZavnRYqC eThwcPY7RkJxCUhFWS1zoFlt85d4zHLCUJxiLUFxFDr0F9L7AOBcDEB6E KJkpun62U+ufmz/kNabhUlZyOrnBWu3HfAaiQ9EliGVFhWmXWIU4iSY46 RHnXSjDApDQGF6wVd1EYVmZSkn53lX2qwUY1wBwJH2fofMAsb2bHjMSsM 4b5C1M5K2V+sZU7LEJnydgkIm84NlOTAtgudrwaAxHHsosEhX2ECUzUFo w75CyWqUlh93FE4oKojT2z8JwO1m9EBw8WyhjG2gjIDvmn2H5yGGVvV9F g==; X-CSE-ConnectionGUID: Ejn4MYkwTnyyTXQz7FKjZw== X-CSE-MsgGUID: xohJ5q78TD+fHwYQQKhIcQ== X-IronPort-AV: E=Sophos;i="6.11,177,1725346800"; d="scan'208";a="35903137" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa1.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 04 Oct 2024 06:20:37 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Fri, 4 Oct 2024 06:20:27 -0700 Received: from DEN-DL-M70577.microchip.com (10.10.85.11) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Fri, 4 Oct 2024 06:20:24 -0700 From: Daniel Machon Date: Fri, 4 Oct 2024 15:19:33 +0200 Subject: [PATCH net-next v2 07/15] net: sparx5: use SPX5_CONST for constants which do not have a symbol MIME-Version: 1.0 Message-ID: <20241004-b4-sparx5-lan969x-switch-driver-v2-7-d3290f581663@microchip.com> References: <20241004-b4-sparx5-lan969x-switch-driver-v2-0-d3290f581663@microchip.com> In-Reply-To: <20241004-b4-sparx5-lan969x-switch-driver-v2-0-d3290f581663@microchip.com> To: "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Lars Povlsen , "Steen Hegelund" , , , , Richard Cochran , , , , , , CC: , , X-Mailer: b4 0.14-dev X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241004_062038_273319_FA2EF396 X-CRM114-Status: GOOD ( 12.11 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Now that we have indentified all the chip constants, update the use of them where a symbol is not defined for the constant. Reviewed-by: Steen Hegelund Signed-off-by: Daniel Machon --- drivers/net/ethernet/microchip/sparx5/sparx5_main.c | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/drivers/net/ethernet/microchip/sparx5/sparx5_main.c b/drivers/net/ethernet/microchip/sparx5/sparx5_main.c index 1fa98158b0a8..6c50d7875207 100644 --- a/drivers/net/ethernet/microchip/sparx5/sparx5_main.c +++ b/drivers/net/ethernet/microchip/sparx5/sparx5_main.c @@ -522,7 +522,7 @@ static int sparx5_init_coreclock(struct sparx5 *sparx5) sparx5, LRN_AUTOAGE_CFG_1); - for (idx = 0; idx < 3; idx++) + for (idx = 0; idx < sparx5->data->consts->n_sio_clks; idx++) spx5_rmw(GCB_SIO_CLOCK_SYS_CLK_PERIOD_SET(clk_period / 100), GCB_SIO_CLOCK_SYS_CLK_PERIOD, sparx5, @@ -550,16 +550,21 @@ static u32 qlim_wm(struct sparx5 *sparx5, int fraction) static int sparx5_qlim_set(struct sparx5 *sparx5) { + const struct sparx5_consts *consts = sparx5->data->consts; u32 res, dp, prio; for (res = 0; res < 2; res++) { for (prio = 0; prio < 8; prio++) spx5_wr(0xFFF, sparx5, - QRES_RES_CFG(prio + 630 + res * 1024)); + QRES_RES_CFG(prio + + consts->qres_max_prio_idx + + res * 1024)); for (dp = 0; dp < 4; dp++) spx5_wr(0xFFF, sparx5, - QRES_RES_CFG(dp + 638 + res * 1024)); + QRES_RES_CFG(dp + + consts->qres_max_colour_idx + + res * 1024)); } /* Set 80,90,95,100% of memory size for top watermarks */ @@ -605,7 +610,7 @@ static int sparx5_start(struct sparx5 *sparx5) int err; /* Setup own UPSIDs */ - for (idx = 0; idx < 3; idx++) { + for (idx = 0; idx < consts->n_own_upsids; idx++) { spx5_wr(idx, sparx5, ANA_AC_OWN_UPSID(idx)); spx5_wr(idx, sparx5, ANA_CL_OWN_UPSID(idx)); spx5_wr(idx, sparx5, ANA_L2_OWN_UPSID(idx));