@@ -9,9 +9,6 @@ title: ASPEED I2C on the AST24XX, AST25XX, and AST26XX SoCs
maintainers:
- Rayn Chen <rayn_chen@aspeedtech.com>
-allOf:
- - $ref: /schemas/i2c/i2c-controller.yaml#
-
properties:
compatible:
enum:
@@ -49,12 +46,50 @@ properties:
description:
states that there is another master active on this bus
+ aspeed,enable-dma:
+ type: boolean
+ description: |
+ I2C bus enable dma mode transfer.
+
+ ASPEED ast2600 platform equipped with 16 I2C controllers that share a
+ single DMA engine. DTS files can specify the data transfer mode to/from
+ the device, either DMA or programmed I/O. However, hardware limitations
+ may require a DTS to manually allocate which controller can use DMA mode.
+ The "aspeed,enable-dma" property allows control of this.
+
+ In cases where one the hardware design results in a specific
+ controller handling a larger amount of data, a DTS would likely
+ enable DMA mode for that one controller.
+
+ aspeed,global-regs:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description: The phandle of i2c global register node.
+
required:
- reg
- compatible
- clocks
- resets
+allOf:
+ - $ref: /schemas/i2c/i2c-controller.yaml#
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: aspeed,ast2600-i2cv2
+
+ then:
+ properties:
+ reg:
+ minItems: 2
+ required:
+ - aspeed,global-regs
+ else:
+ properties:
+ aspeed,global-regs: false
+ aspeed,enable-dma: false
+
unevaluatedProperties: false
examples:
@@ -71,3 +106,13 @@ examples:
interrupts = <0>;
interrupt-parent = <&i2c_ic>;
};
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ i2c1: i2c@80 {
+ compatible = "aspeed,ast2600-i2cv2";
+ reg = <0x80 0x80>, <0xc00 0x20>;
+ aspeed,global-regs = <&i2c_global>;
+ clocks = <&syscon ASPEED_CLK_APB>;
+ resets = <&syscon ASPEED_RESET_I2C>;
+ interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
+ };