From patchwork Tue Oct 8 13:20:50 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dhruva Gole X-Patchwork-Id: 13826485 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 76EA8CEF172 for ; Tue, 8 Oct 2024 13:29:17 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Type: Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date :Subject:CC:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=QYzjg0JtoUXsOQhKtNf2LqrnhQLJUpr57FfxPtZIwj8=; b=JlKCunrvZKQQjMPbBnmN+o0hr0 O9C3i1kx/Uv/cVtf1bxWx2E09XeuI0GiZhzMTwLGZNc/KW+vBqpKUYc+yNSnAevtMsyrK3EOygEw6 0wc/fZYBt8WcFJq0d321yWjXeSZ+ANYSwqiVy4U2tAVUdRQIguUM+l6JmsKBEyryIjoXBN5b9ETyD /PLsvSM9PNjjZ7GN9slpX8wem1eSKIYOV6VNd70FA5objELgjgoTnnqT68nIwynqdIR/qtrQIev/6 +ydh82iucNH5TyEaY28JHMs/QniM/CPl+8LumnT/+vc1P7kEX/W5+dcNNgvtX2oHSalT1DVstgPwV unOMvytw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1syAGw-00000005zRA-3Xyz; Tue, 08 Oct 2024 13:29:06 +0000 Received: from fllv0015.ext.ti.com ([198.47.19.141]) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1syABY-00000005xz8-07sF for linux-arm-kernel@lists.infradead.org; Tue, 08 Oct 2024 13:23:33 +0000 Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 498DNM30056165; Tue, 8 Oct 2024 08:23:22 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1728393802; bh=QYzjg0JtoUXsOQhKtNf2LqrnhQLJUpr57FfxPtZIwj8=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=papME3lZItZeRRVOImhp6KCq/h96JBJUcEJJzsHwH172Wp3l/jtUW64kHUJOA/sNi iJF6+sVqRHoPUrqeeiz3fHivxtKeFAueeQLGWQwrr0HPoojIdExGlJrSwFxo5FGAZj oVS4CE7rYcRS9v0BUUzFMih0RrBHuMCzf6VHxBDI= Received: from DLEE115.ent.ti.com (dlee115.ent.ti.com [157.170.170.26]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 498DNMif097948 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 8 Oct 2024 08:23:22 -0500 Received: from DLEE115.ent.ti.com (157.170.170.26) by DLEE115.ent.ti.com (157.170.170.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Tue, 8 Oct 2024 08:23:21 -0500 Received: from lelvsmtp6.itg.ti.com (10.180.75.249) by DLEE115.ent.ti.com (157.170.170.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Tue, 8 Oct 2024 08:23:21 -0500 Received: from lcpd911.dhcp.ti.com (lcpd911.dhcp.ti.com [172.24.227.226]) by lelvsmtp6.itg.ti.com (8.15.2/8.15.2) with ESMTP id 498DN82D098273; Tue, 8 Oct 2024 08:23:19 -0500 From: Dhruva Gole To: Nishanth Menon , Vignesh Raghavendra , Tero Kristo CC: , , , , Dhruva Gole , Rob Herring , Krzysztof Kozlowski , Bryan Brattlof Subject: [PATCH V8 1/4] arm64: dts: ti: k3-am62a: add opp frequencies Date: Tue, 8 Oct 2024 18:50:50 +0530 Message-ID: <20241008132052.407994-2-d-gole@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241008132052.407994-1-d-gole@ti.com> References: <20241008132052.407994-1-d-gole@ti.com> MIME-Version: 1.0 X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241008_062332_190983_04A4D3FB X-CRM114-Status: GOOD ( 11.87 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Bryan Brattlof One power management technique available to the Cortex-A53s is their ability to dynamically scale their frequency across the device's Operating Performance Points (OPP) The OPPs available for the Cortex-A53s on the AM62Ax can vary based on the silicon variant used. The SoC variant is encoded into the WKUP_MMR0_WKUP0_CTRL_MMR0_JTAG_USER_ID register which is used to limit to only OPP entries the variant supports. A table of all these variants can be found in it's data sheet[0] for the AM62Ax family. Add the OPP table into the SoC's fdti file along with the syscon node to describe the WKUP_MMR0_WKUP0_CTRL_MMR0_JTAG_USER_ID register to detect the SoC variant. [0] https://www.ti.com/lit/ds/symlink/am62a3.pdf Signed-off-by: Bryan Brattlof Signed-off-by: Dhruva Gole --- arch/arm64/boot/dts/ti/k3-am62a-wakeup.dtsi | 5 ++ arch/arm64/boot/dts/ti/k3-am62a7.dtsi | 51 +++++++++++++++++++++ 2 files changed, 56 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am62a-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-am62a-wakeup.dtsi index f5ac101a04df..0b1dd5390cd3 100644 --- a/arch/arm64/boot/dts/ti/k3-am62a-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62a-wakeup.dtsi @@ -17,6 +17,11 @@ chipid: chipid@14 { reg = <0x14 0x4>; }; + opp_efuse_table: syscon@18 { + compatible = "ti,am62-opp-efuse-table", "syscon"; + reg = <0x18 0x4>; + }; + cpsw_mac_syscon: ethernet-mac-syscon@200 { compatible = "ti,am62p-cpsw-mac-efuse", "syscon"; reg = <0x200 0x8>; diff --git a/arch/arm64/boot/dts/ti/k3-am62a7.dtsi b/arch/arm64/boot/dts/ti/k3-am62a7.dtsi index f86a23404e6d..6c99221beb6b 100644 --- a/arch/arm64/boot/dts/ti/k3-am62a7.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62a7.dtsi @@ -48,6 +48,8 @@ cpu0: cpu@0 { d-cache-line-size = <64>; d-cache-sets = <128>; next-level-cache = <&L2_0>; + operating-points-v2 = <&a53_opp_table>; + clocks = <&k3_clks 135 0>; }; cpu1: cpu@1 { @@ -62,6 +64,8 @@ cpu1: cpu@1 { d-cache-line-size = <64>; d-cache-sets = <128>; next-level-cache = <&L2_0>; + operating-points-v2 = <&a53_opp_table>; + clocks = <&k3_clks 136 0>; }; cpu2: cpu@2 { @@ -76,6 +80,8 @@ cpu2: cpu@2 { d-cache-line-size = <64>; d-cache-sets = <128>; next-level-cache = <&L2_0>; + operating-points-v2 = <&a53_opp_table>; + clocks = <&k3_clks 137 0>; }; cpu3: cpu@3 { @@ -90,6 +96,51 @@ cpu3: cpu@3 { d-cache-line-size = <64>; d-cache-sets = <128>; next-level-cache = <&L2_0>; + operating-points-v2 = <&a53_opp_table>; + clocks = <&k3_clks 138 0>; + }; + }; + + a53_opp_table: opp-table { + compatible = "operating-points-v2-ti-cpu"; + opp-shared; + syscon = <&opp_efuse_table>; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + opp-supported-hw = <0x01 0x0007>; + clock-latency-ns = <6000000>; + }; + + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + opp-supported-hw = <0x01 0x0007>; + clock-latency-ns = <6000000>; + }; + + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-supported-hw = <0x01 0x0007>; + clock-latency-ns = <6000000>; + }; + + opp-800000000 { + opp-hz = /bits/ 64 <800000000>; + opp-supported-hw = <0x01 0x0007>; + clock-latency-ns = <6000000>; + }; + + opp-1000000000 { + opp-hz = /bits/ 64 <1000000000>; + opp-supported-hw = <0x01 0x0006>; + clock-latency-ns = <6000000>; + }; + + opp-1250000000 { + opp-hz = /bits/ 64 <1250000000>; + opp-supported-hw = <0x01 0x0004>; + clock-latency-ns = <6000000>; + opp-suspend; }; };