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Thu, 10 Oct 2024 16:28:07 +0200 From: Amelie Delaunay Date: Thu, 10 Oct 2024 16:27:52 +0200 Subject: [PATCH 02/11] dmaengine: stm32-dma3: prevent pack/unpack thanks to DT configuration MIME-Version: 1.0 Message-ID: <20241010-dma3-mp25-updates-v1-2-adf0633981ea@foss.st.com> References: <20241010-dma3-mp25-updates-v1-0-adf0633981ea@foss.st.com> In-Reply-To: <20241010-dma3-mp25-updates-v1-0-adf0633981ea@foss.st.com> To: Vinod Koul , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue CC: , , , , , Amelie Delaunay X-Mailer: b4 0.14.2 X-Originating-IP: [10.252.31.182] X-ClientProxiedBy: SHFCAS1NODE1.st.com (10.75.129.72) To SHFDAG1NODE3.st.com (10.75.129.71) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241010_153143_418681_159476C3 X-CRM114-Status: GOOD ( 12.95 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org When source data width/burst and destination data width/burst are different, data are packed or unpacked in DMA3 channel FIFO, using CxTR1.PAM. Data are pushed out from DMA3 channel FIFO when the destination burst length (= data width * burst) is reached. If the transfer is stopped before CxBR1.BNDT = 0, and if some bytes are packed/unpacked in the DMA3 channel FIFO, these bytes are lost. Indeed, DMA3 channel FIFO has no flush capability, only reset. To avoid potential bytes lost, pack/unpack must be prevented by setting memory data width/burst equal to peripheral data width/burst. Memory accesses will be penalized. But it is the only way to avoid bytes lost. Prevent pack/unpack feature can be activated by setting bit 16 of DMA3 Transfer requirements bitfield (tr_conf) in device tree. Signed-off-by: Amelie Delaunay --- drivers/dma/stm32/stm32-dma3.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/dma/stm32/stm32-dma3.c b/drivers/dma/stm32/stm32-dma3.c index 0be6e944df6fd5d2a02974085251549d9389a37e..2b4cc479e1a1206fef7fd2808d1342048d81e07b 100644 --- a/drivers/dma/stm32/stm32-dma3.c +++ b/drivers/dma/stm32/stm32-dma3.c @@ -221,6 +221,7 @@ enum stm32_dma3_port_data_width { #define STM32_DMA3_DT_BREQ BIT(8) /* CTR2_BREQ */ #define STM32_DMA3_DT_PFREQ BIT(9) /* CTR2_PFREQ */ #define STM32_DMA3_DT_TCEM GENMASK(13, 12) /* CTR2_TCEM */ +#define STM32_DMA3_DT_NOPACK BIT(16) /* CTR1_PAM */ /* struct stm32_dma3_chan .config_set bitfield */ #define STM32_DMA3_CFG_SET_DT BIT(0) @@ -622,6 +623,10 @@ static int stm32_dma3_chan_prep_hw(struct stm32_dma3_chan *chan, enum dma_transf /* Set source (memory) data width and burst */ sdw = stm32_dma3_get_max_dw(chan->max_burst, sap_max_dw, len, src_addr); sbl_max = stm32_dma3_get_max_burst(len, sdw, chan->max_burst); + if (!!FIELD_GET(STM32_DMA3_DT_NOPACK, tr_conf)) { + sdw = ddw; + sbl_max = dbl_max; + } _ctr1 |= FIELD_PREP(CTR1_SDW_LOG2, ilog2(sdw)); _ctr1 |= FIELD_PREP(CTR1_SBL_1, sbl_max - 1); @@ -652,6 +657,11 @@ static int stm32_dma3_chan_prep_hw(struct stm32_dma3_chan *chan, enum dma_transf /* Set destination (memory) data width and burst */ ddw = stm32_dma3_get_max_dw(chan->max_burst, dap_max_dw, len, dst_addr); dbl_max = stm32_dma3_get_max_burst(len, ddw, chan->max_burst); + if (!!FIELD_GET(STM32_DMA3_DT_NOPACK, tr_conf) || + ((_ctr2 & CTR2_PFREQ) && ddw > sdw)) { /* Packing to wider ddw not supported */ + ddw = sdw; + dbl_max = sbl_max; + } _ctr1 |= FIELD_PREP(CTR1_SDW_LOG2, ilog2(sdw)); _ctr1 |= FIELD_PREP(CTR1_SBL_1, sbl_max - 1);