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This way, 74.25MHz clock frequency specified in panel-timing node may accommodate 7-fold 519.75MHz "media_ldb" clock which is derived from 1.0395GHz "video_pll1" clock. This should suppress this LDB driver warning: [ 17.923709] fsl-ldb 32ec0000.blk-ctrl:bridge@5c: Configured LDB clock (72400000 Hz) does not match requested LVDS clock: 506800000 Hz This also makes the display mode used by the panel pass mode validation against pixel clock rate and "media_ldb" clock rate in a certain display driver. Fixes: 326d86e197fc ("arm64: dts: imx8mp-phyboard-pollux-rdk: add etml panel support") Signed-off-by: Liu Ying --- v2: * No change. .../dts/freescale/imx8mp-phyboard-pollux-rdk.dts | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts b/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts index 50debe821c42..20cb5363cccb 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts @@ -37,6 +37,21 @@ panel1_lvds: panel-lvds { backlight = <&backlight_lvds>; power-supply = <®_vcc_3v3_sw>; + panel-timing { + clock-frequency = <74250000>; + hactive = <1280>; + vactive = <800>; + hfront-porch = <72>; + hback-porch = <86>; + hsync-len = <2>; + vfront-porch = <15>; + vback-porch = <21>; + vsync-len = <2>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + }; + port { panel1_in: endpoint { remote-endpoint = <&ldb_lvds_ch1>;