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Mon, 14 Oct 2024 13:07:37 +0000 (UTC) Received: from dovecot-director2.suse.de ([2a07:de40:b281:106:10:150:64:167]) by imap1.dmz-prg2.suse.org with ESMTPSA id eLgpMpkXDWcqTwAAD6G6ig (envelope-from ); Mon, 14 Oct 2024 13:07:37 +0000 From: Stanimir Varbanov To: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rpi-kernel@lists.infradead.org, linux-pci@vger.kernel.org, Broadcom internal kernel review list Cc: Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Florian Fainelli , Jim Quinlan , Nicolas Saenz Julienne , Bjorn Helgaas , Lorenzo Pieralisi , kw@linux.com, Philipp Zabel , Andrea della Porta , Phil Elwell , Jonathan Bell , Stanimir Varbanov Subject: [PATCH v3 06/11] PCI: brcmstb: Avoid turn off of bridge reset Date: Mon, 14 Oct 2024 16:07:05 +0300 Message-ID: <20241014130710.413-7-svarbanov@suse.de> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241014130710.413-1-svarbanov@suse.de> References: <20241014130710.413-1-svarbanov@suse.de> MIME-Version: 1.0 X-Rspamd-Queue-Id: D71E421D47 X-Spamd-Result: default: False [-1.51 / 50.00]; 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Signed-off-by: Stanimir Varbanov --- v2 -> v3: - Added more descriptive comment on CFG_QUIRK_AVOID_BRIDGE_SHUTDOWN quirk. drivers/pci/controller/pcie-brcmstb.c | 17 +++++++++++++++-- 1 file changed, 15 insertions(+), 2 deletions(-) diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/controller/pcie-brcmstb.c index b76c16287f37..757a1646d53c 100644 --- a/drivers/pci/controller/pcie-brcmstb.c +++ b/drivers/pci/controller/pcie-brcmstb.c @@ -234,10 +234,20 @@ struct inbound_win { u64 cpu_addr; }; +/* + * The RESCAL block is tied to PCIe controller #1, regardless of the number of + * controllers, and turning off PCIe controller #1 prevents access to the RESCAL + * register blocks, therefore not other controller can access this register + * space, and depending upon the bus fabric we may get a timeout (UBUS/GISB), + * or a hang (AXI). + */ +#define CFG_QUIRK_AVOID_BRIDGE_SHUTDOWN BIT(0) + struct pcie_cfg_data { const int *offsets; const enum pcie_soc_base soc_base; const bool has_phy; + const u32 quirks; u8 num_inbound_wins; int (*perst_set)(struct brcm_pcie *pcie, u32 val); int (*bridge_sw_init_set)(struct brcm_pcie *pcie, u32 val); @@ -290,6 +300,7 @@ struct brcm_pcie { struct subdev_regulators *sr; bool ep_wakeup_capable; bool has_phy; + u32 quirks; u8 num_inbound_wins; }; @@ -1539,8 +1550,9 @@ static int brcm_pcie_turn_off(struct brcm_pcie *pcie) u32p_replace_bits(&tmp, 1, PCIE_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_MASK); writel(tmp, base + HARD_DEBUG(pcie)); - /* Shutdown PCIe bridge */ - ret = pcie->bridge_sw_init_set(pcie, 1); + if (!(pcie->quirks & CFG_QUIRK_AVOID_BRIDGE_SHUTDOWN)) + /* Shutdown PCIe bridge */ + ret = pcie->bridge_sw_init_set(pcie, 1); return ret; } @@ -1854,6 +1866,7 @@ static int brcm_pcie_probe(struct platform_device *pdev) pcie->perst_set = data->perst_set; pcie->bridge_sw_init_set = data->bridge_sw_init_set; pcie->has_phy = data->has_phy; + pcie->quirks = data->quirks; pcie->num_inbound_wins = data->num_inbound_wins; pcie->base = devm_platform_ioremap_resource(pdev, 0);