From patchwork Tue Oct 15 12:14:37 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Amelie Delaunay X-Patchwork-Id: 13836304 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0A5E2D21684 for ; Tue, 15 Oct 2024 12:19:24 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:CC:To:In-Reply-To:References :Message-ID:Content-Transfer-Encoding:Content-Type:MIME-Version:Subject:Date: From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=1FmGrSANQn07iSNnWCRz9WCfIaMI09hSsfRbqu2gnOU=; b=A8dW7fU2uT/cgZiMHO1kZ/0X7Y kzNNpftdmJkSux+ZefbHv3ybaPL3RTsZL2AulyaO8A1Wkm7RV4QXfARXhWmAfuPeJTiD23Jg5jU+C o58leV7OdU1o1GJF2rXoqD+rWNIxmfFsokNLD3zxtvTHUqc62iv0AXcmCKjZA/xVGGiiTk9WZM+3X ybHNcTF9PzzZ9cqvjg2H2a+7sDuZDU3t922O4f/IV1diMZ1CgGyjgnCp/2YW/vzvp4u2+IXdbp8Gc ETcaZEf7/JAHCt4A5PFFUu5tzjUViq4DWG1Bhu5ilogP3PK5cApnrmozUDIW1R/U7yv907rr1jTct w+PLbjvA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1t0gW8-000000088g0-2Y76; Tue, 15 Oct 2024 12:19:12 +0000 Received: from mx07-00178001.pphosted.com ([185.132.182.106]) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1t0gTP-000000087tb-1U5D for linux-arm-kernel@lists.infradead.org; Tue, 15 Oct 2024 12:16:24 +0000 Received: from pps.filterd (m0241204.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 49F8bYfA027894; Tue, 15 Oct 2024 14:16:16 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=selector1; bh= 1FmGrSANQn07iSNnWCRz9WCfIaMI09hSsfRbqu2gnOU=; b=i+EpCeJP2v5lQoKP 7wHXFfPiAb0MUdQuYdomotUyZGBeM3pWQhTsJz7KvjBqh8qg+8N7owPlycG9D/Uh l5akDnfr+1U+B81/BrulzujahyC1ij3h5eEUPTtyJXuXHuiJdzKxHGTEY+o2DA02 ek3J2DIa+YrcnoETc85jrpccnTkJHlsDi6S22hsFiZ8KMQG86vTdoJD3t7OGF0p6 hd0fY84V4HJpfbiIngHCdXo/1tQUnG/5hamgUBJJquiBrNYQT3a8IvcS92V6c5sY cy8mobAO4dO7ccFKQuvAjGk6P3McC9T+zTaHVInYrwTG+OR/IFd9gFMIPb6ebkf1 jQV8zQ== Received: from beta.dmz-ap.st.com (beta.dmz-ap.st.com [138.198.100.35]) by mx07-00178001.pphosted.com (PPS) with ESMTPS id 427gewwakg-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 15 Oct 2024 14:16:16 +0200 (MEST) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id 084CB4004F; Tue, 15 Oct 2024 14:15:28 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node3.st.com [10.75.129.71]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 4CA2322233B; Tue, 15 Oct 2024 14:14:47 +0200 (CEST) Received: from localhost (10.48.87.35) by SHFDAG1NODE3.st.com (10.75.129.71) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.37; Tue, 15 Oct 2024 14:14:47 +0200 From: Amelie Delaunay Date: Tue, 15 Oct 2024 14:14:37 +0200 Subject: [PATCH v2 1/9] dt-bindings: dma: stm32-dma3: prevent packing/unpacking mode MIME-Version: 1.0 Message-ID: <20241015-dma3-mp25-updates-v2-1-b63e21556ec8@foss.st.com> References: <20241015-dma3-mp25-updates-v2-0-b63e21556ec8@foss.st.com> In-Reply-To: <20241015-dma3-mp25-updates-v2-0-b63e21556ec8@foss.st.com> To: Vinod Koul , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue CC: , , , , , Amelie Delaunay X-Mailer: b4 0.14.2 X-Originating-IP: [10.48.87.35] X-ClientProxiedBy: EQNCAS1NODE4.st.com (10.75.129.82) To SHFDAG1NODE3.st.com (10.75.129.71) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241015_051623_731236_5028A162 X-CRM114-Status: GOOD ( 10.50 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org When source data width/burst and destination data width/burst are different, data are packed or unpacked in DMA3 channel FIFO. Data are pushed out from DMA3 channel FIFO when the destination burst length (= data width * burst) is reached. If the channel is stopped before the transfer end, and if some bytes are packed/unpacked in the DMA3 channel FIFO, these bytes are lost. Indeed, DMA3 channel FIFO has no flush capability, only reset. To avoid potential bytes lost, pack/unpack must be prevented by setting memory data width/burst equal to peripheral data width/burst. Memory accesses will be penalized. But it is the only way to avoid bytes lost. Some devices (e.g. cyclic RX like UART) need this, so add the possibility to prevent pack/unpack feature, by setting bit 16 of the 'DMA transfer requirements' bit mask. Acked-by: Rob Herring (Arm) Signed-off-by: Amelie Delaunay --- Documentation/devicetree/bindings/dma/stm32/st,stm32-dma3.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/dma/stm32/st,stm32-dma3.yaml b/Documentation/devicetree/bindings/dma/stm32/st,stm32-dma3.yaml index 7fdc44b2e6467928622a5bb25d9e0c74bb1790ae..5484848735f8ac3d2050104bbab1d986e82ba6a7 100644 --- a/Documentation/devicetree/bindings/dma/stm32/st,stm32-dma3.yaml +++ b/Documentation/devicetree/bindings/dma/stm32/st,stm32-dma3.yaml @@ -96,6 +96,9 @@ properties: including the update of the LLI if any 0x3: at channel level, the transfer complete event is generated at the end of the last LLI + -bit 16: Prevent packing/unpacking mode + 0x0: pack/unpack enabled when source data width/burst != destination data width/burst + 0x1: memory data width/burst forced to peripheral data width/burst to prevent pack/unpack required: - compatible