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[RFC,1/2] dt-bindings: iommu: arm,smmu-v3: introduce nxp,imx95-bypass-sid-zero

Message ID 20241015-smmuv3-v1-1-e4b9ed1b5501@nxp.com (mailing list archive)
State New, archived
Headers show
Series iommu/arm-smmu-v3: bypass streamid zero on i.MX95 | expand

Commit Message

Peng Fan (OSS) Oct. 15, 2024, 3:14 a.m. UTC 
From: Peng Fan <peng.fan@nxp.com>

i.MX95 eDMA3 connects to DSU ACP, supporting dma coherent memory to
memory operations. However TBU is in the path between eDMA3 and ACP,
need to bypass the default SID 0 to make eDMA3 work properly.

Introduce the property "nxp,imx95-bypass-sid-zero" for bypassing SID 0.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml | 4 ++++
 1 file changed, 4 insertions(+)
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Patch

diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml b/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml
index 75fcf4cb52d9f6449238578f20288966af35cab3..88ab908154e31aabf98f3bbe4df348956f49d5e1 100644
--- a/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml
+++ b/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml
@@ -69,6 +69,10 @@  properties:
       register access with page 0 offsets. Set for Cavium ThunderX2 silicon that
       doesn't support SMMU page1 register space.
 
+  nxp,imx95-bypass-sid-zero:
+    type: boolean
+    description: StreamID 0 that needs transaction set as bypass mode.
+
 required:
   - compatible
   - reg