From patchwork Tue Oct 15 21:02:04 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Igor Belwon X-Patchwork-Id: 13837092 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id AEBD1D1D876 for ; Tue, 15 Oct 2024 21:09:58 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:Cc:To:From: Reply-To:Content-Type:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=ByFmW5jKAzcO83qrdG8K7fnIfxXj7zf5so/VP1aQtAE=; b=j0HmV4DXEEZHR0gnMcsP+Ju5uC xk9fDnbl3AOQdcqlNFDnJxqTvJS7TnVr+RUWP3A7ENbR9tqFENzCY9iG/Z5EO23X1/RTgI60jO74Q WNbmD9nCfQ6jhufSN/3liTCoPK2TGWG1x556O10B0TOupxOa4roQTgEo7OQkn5fo8xSYOatBJ4Ct0 z6wcOLqed575Tzk3S+pmWVLlDIHgy8qYezQJwNN+24OdT1TUjtNBsT7dfx4YUIu79f/XEwj3OzDIt Mu8Oz1kRMEU+1TakNQzGxECD/50MmN12F9TYTOOEmP6lapwraFB+E6PWEXC9AJV2Bpv7G4U5rZGti E0tCbzfw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1t0onZ-00000009b1t-2TYw; Tue, 15 Oct 2024 21:09:45 +0000 Received: from out-02.smtp.spacemail.com ([63.250.43.87]) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1t0ogb-00000009ZMA-3uOB for linux-arm-kernel@lists.infradead.org; Tue, 15 Oct 2024 21:02:35 +0000 Received: from prod-lbout-phx.jellyfish.systems (unknown [198.177.122.3]) by smtp.spacemail.com (Postfix) with ESMTPA id 4XSmkw6wDfz4wgK; Tue, 15 Oct 2024 21:02:32 +0000 (UTC) Received: from igor-systemproductname.lan (83.8.240.202.ipv4.supernova.orange.pl [83.8.240.202]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by mail.spacemail.com (Postfix) with ESMTPSA id 4XSmkn4HbCz8sWT; Tue, 15 Oct 2024 21:02:25 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=mentallysanemainliners.org; s=spacemail; t=1729026147; bh=6jq72hVNwLzr/2NapVqA51w6jpOXYCGl9aLMLQa9Nf0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=B9ojBWkrkhBdHnLuGrxEjS8ugf3EPERNZXuQzN/ueBsMWSuKVQ2TtMG4XumTgTuPR zUq/jQ/uKECPRz8y0SCNeYr1QKlFeHtwbIiXMBUKaszXUoEF6+ZA1l5ne/PtOe8KGL FMfsBscp15SslmO8zSj+DnxbpMQW8VAsDZJbcLjzhOcqHExKSIea3QlvcSmz6Og8Ja hKqOztMp4pU4hGYrFcAi5ec4C4MiNZ/zQ8KoaP2XHVVss2Z7iUY30c1Wr35SqHf1u7 yWclG8krCsPIZYtFwtAhesr1oqK6/dyFqLxU50qXv4+SyyswMN/m5nvJBls7Pkjg4K LZ8E5JW3WldTQ== From: Igor Belwon To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Alim Akhtar , David Wronek , Sibi Sankar , Ivaylo Ivanov Cc: linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 5/6] arm64: dts: exynos: Add initial support for the Exynos 990 SoC Date: Tue, 15 Oct 2024 23:02:04 +0200 Message-ID: <20241015210205.963931-6-igor.belwon@mentallysanemainliners.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241015210205.963931-1-igor.belwon@mentallysanemainliners.org> References: <20241015210205.963931-1-igor.belwon@mentallysanemainliners.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241015_140234_129907_72EE186B X-CRM114-Status: GOOD ( 15.18 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The Exynos 990 SoC is an ARMv8 mobile SoC found in Samsung Galaxy N/S20 series phones (x1sxxx, c1sxxx). Add minimal support for this SoC, including: - All 8 cores via PSCI - ChipID - Generic timer. The devices using this SoC suffer from the same issue as Exynos 8895 caused by the stock Samsung bootloader, as it doesn't configure CNTFRQ_EL0. Hence it's needed to hardcode the adequate frequency in the timer node, otherwise the kernel panics. Signed-off-by: Igor Belwon --- arch/arm64/boot/dts/exynos/exynos990.dtsi | 194 ++++++++++++++++++++++ 1 file changed, 194 insertions(+) create mode 100644 arch/arm64/boot/dts/exynos/exynos990.dtsi diff --git a/arch/arm64/boot/dts/exynos/exynos990.dtsi b/arch/arm64/boot/dts/exynos/exynos990.dtsi new file mode 100644 index 000000000000..16fda5fe8163 --- /dev/null +++ b/arch/arm64/boot/dts/exynos/exynos990.dtsi @@ -0,0 +1,194 @@ +// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause +/* + * Samsung Exynos 990 SoC device tree source + * + * Copyright (c) 2024, Igor Belwon + */ + +#include + +/ { + compatible = "samsung,exynos990"; + #address-cells = <2>; + #size-cells = <1>; + + interrupt-parent = <&gic>; + + arm-a55-pmu { + compatible = "arm,cortex-a55-pmu"; + interrupts = , + , + , + ; + + interrupt-affinity = <&cpu0>, + <&cpu1>, + <&cpu2>, + <&cpu3>; + }; + + arm-a76-pmu { + compatible = "arm,cortex-a76-pmu"; + interrupts = , + ; + + interrupt-affinity = <&cpu4>, + <&cpu5>; + }; + + /* There's no PMU model for cluster2, which are the Mongoose cores. */ + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu-map { + cluster0 { + core0 { + cpu = <&cpu0>; + }; + + core1 { + cpu = <&cpu1>; + }; + + core2 { + cpu = <&cpu2>; + }; + + core3 { + cpu = <&cpu3>; + }; + }; + + cluster1 { + core0 { + cpu = <&cpu4>; + }; + + core1 { + cpu = <&cpu5>; + }; + }; + + cluster2 { + core0 { + cpu = <&cpu6>; + }; + + core1 { + cpu = <&cpu7>; + }; + }; + }; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x0>; + enable-method = "psci"; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x1>; + enable-method = "psci"; + }; + + cpu2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x2>; + enable-method = "psci"; + }; + + cpu3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x3>; + enable-method = "psci"; + }; + + cpu4: cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a76"; + reg = <0x4>; + enable-method = "psci"; + }; + + cpu5: cpu@101 { + device_type = "cpu"; + compatible = "arm,cortex-a76"; + reg = <0x5>; + enable-method = "psci"; + }; + + cpu6: cpu@200 { + device_type = "cpu"; + compatible = "samsung,mongoose-m5"; + reg = <0x6>; + enable-method = "psci"; + }; + + cpu7: cpu@201 { + device_type = "cpu"; + compatible = "samsung,mongoose-m5"; + reg = <0x7>; + enable-method = "psci"; + }; + }; + + oscclk: clock-osc { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-output-names = "oscclk"; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "hvc"; + }; + + soc: soc@0 { + compatible = "simple-bus"; + ranges = <0x0 0x0 0x0 0x20000000>; + + #address-cells = <1>; + #size-cells = <1>; + + chipid@10000000 { + compatible = "samsung,exynos990-chipid", + "samsung,exynos850-chipid"; + reg = <0x10000000 0x100>; + }; + + gic: interrupt-controller@10101000 { + compatible = "arm,gic-400"; + reg = <0x10101000 0x1000>, + <0x10102000 0x1000>, + <0x10104000 0x2000>, + <0x10106000 0x2000>; + #interrupt-cells = <3>; + interrupt-controller; + interrupts = ; + #address-cells = <0>; + #size-cells = <1>; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + + /* + * Non-updatable, broken stock Samsung bootloader does not + * configure CNTFRQ_EL0 + */ + clock-frequency = <26000000>; + }; +};