@@ -998,7 +998,7 @@ mlb: mlb@218c000 {
};
usdhc1: mmc@2190000 {
- compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc";
+ compatible = "fsl,imx6sx-usdhc";
reg = <0x02190000 0x4000>;
interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6SX_CLK_USDHC1>,
@@ -1012,7 +1012,7 @@ usdhc1: mmc@2190000 {
};
usdhc2: mmc@2194000 {
- compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc";
+ compatible = "fsl,imx6sx-usdhc";
reg = <0x02194000 0x4000>;
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6SX_CLK_USDHC2>,
@@ -1026,7 +1026,7 @@ usdhc2: mmc@2194000 {
};
usdhc3: mmc@2198000 {
- compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc";
+ compatible = "fsl,imx6sx-usdhc";
reg = <0x02198000 0x4000>;
interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6SX_CLK_USDHC3>,
@@ -1040,7 +1040,7 @@ usdhc3: mmc@2198000 {
};
usdhc4: mmc@219c000 {
- compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc";
+ compatible = "fsl,imx6sx-usdhc";
reg = <0x0219c000 0x4000>;
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6SX_CLK_USDHC4>,