From patchwork Fri Oct 25 08:28:27 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?TElBTktVTiBZQU5HICjmnajov57lnaQp?= X-Patchwork-Id: 13850208 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 52AFED0C5E3 for ; Fri, 25 Oct 2024 08:34:41 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Type: Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date :Subject:CC:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=jHk7k0mLNr2tL+X1mT3LjPHy3SzInMKuWg8T+fWq1Bs=; b=1JIXlWGes/Hl/uuJjeCm6CstTy C3C2IbPzzJ+YyLVbjqIRaeAdTmpOi/04IZLcoaTUejSunLdPVO8JVeukxG3Z2dbD4o91FmH2jQkLN OK7iHBNj80nb2vWSnb/jJMikoYp9BAL6nNx8cc06qz4s826ozjjtr8yY4r9Biep+KwYX/Z8k1dWn5 sz1R8JUQhfBFzXGAeKVTUCO+cfqa0dirGMnsVXgGqOEPVuZub6QyvuD+lFtYEe6EqzB6iBio1gwOB ZxNqVhwYdtD8dsaPyNwzlJdF1sL+cbXNt5tWLgbzKhTyWxxLYeXznRK6KAZo2/ydWPz81j7KQqORa o7ZSe4WQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1t4Fm9-00000002ziG-3IUp; Fri, 25 Oct 2024 08:34:29 +0000 Received: from mailgw01.mediatek.com ([216.200.240.184]) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1t4Fjg-00000002zFL-0hk4; Fri, 25 Oct 2024 08:31:58 +0000 X-UUID: 9323af6092ab11ef82ff63e91e7eb18c-20241025 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=jHk7k0mLNr2tL+X1mT3LjPHy3SzInMKuWg8T+fWq1Bs=; b=Z4CPxdB6x9O2woEeRVDZeQlG06ZZl9nQlyV3vTo5Y4nVAdCk1E0rmr8Y/fR3cVTil/l5KCfjhH/ZvV0HSq+vPRA+zS1atyqGw43nIde/Wi7snaqMr7bwrrn+mdzmRzrzmq3h8eCa80hg8NMZPyRAS8Q/JqHBywC24tqL/gdYGuk=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.42,REQID:9c4790e7-0e7e-48ec-bcf4-99a3b4a3512c,IP:0,U RL:0,TC:0,Content:-5,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION :release,TS:-5 X-CID-META: VersionHash:b0fcdc3,CLOUDID:6d60dacc-110e-4f79-849e-58237df93e70,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:1,File:nil,RT:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0,LES:1, SPR:NO,DKR:0,DKP:0,BRR:0,BRE:0,ARC:0 X-CID-BVR: 0,NGT X-CID-BAS: 0,NGT,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR,TF_CID_SPAM_ULS X-UUID: 9323af6092ab11ef82ff63e91e7eb18c-20241025 Received: from mtkmbs09n1.mediatek.inc [(172.21.101.35)] by mailgw01.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 144732581; Fri, 25 Oct 2024 01:31:47 -0700 Received: from mtkmbs11n1.mediatek.inc (172.21.101.185) by mtkmbs11n1.mediatek.inc (172.21.101.185) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Fri, 25 Oct 2024 16:31:44 +0800 Received: from mszsdclx1211.gcn.mediatek.inc (10.16.7.31) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Fri, 25 Oct 2024 16:31:44 +0800 From: Liankun Yang To: , , , , , , , , , , , , , , , CC: , , , Subject: [PATCH v2 1/3] drm/mediatek: Fix YCbCr422 color format issue for DP Date: Fri, 25 Oct 2024 16:28:27 +0800 Message-ID: <20241025083036.8829-2-liankun.yang@mediatek.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241025083036.8829-1-liankun.yang@mediatek.com> References: <20241025083036.8829-1-liankun.yang@mediatek.com> MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241025_013156_263653_ABAD5591 X-CRM114-Status: GOOD ( 11.49 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Setting up misc0 for Pixel Encoding Format. According to the definition of YCbCr in spec 1.2a Table 2-96, 0x1 << 1 should be written to the register. Use switch case to distinguish RGB, YCbCr422, and unsupported color formats. Fixes: f70ac097a2cf ("drm/mediatek: Add MT8195 Embedded DisplayPort driver") Signed-off-by: Liankun Yang --- Change in V2 - Modify the value written to the register Per suggestion from the previous thread: https://patchwork.kernel.org/project/linux-mediatek/patch/20240510021810.19302-1-liankun.yang@mediatek.com/ --- drivers/gpu/drm/mediatek/mtk_dp.c | 13 ++++++++----- 1 file changed, 8 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_dp.c b/drivers/gpu/drm/mediatek/mtk_dp.c index f0f6f402994a..613e1c842478 100644 --- a/drivers/gpu/drm/mediatek/mtk_dp.c +++ b/drivers/gpu/drm/mediatek/mtk_dp.c @@ -460,18 +460,16 @@ static int mtk_dp_set_color_format(struct mtk_dp *mtk_dp, enum dp_pixelformat color_format) { u32 val; - - /* update MISC0 */ - mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_3034, - color_format << DP_TEST_COLOR_FORMAT_SHIFT, - DP_TEST_COLOR_FORMAT_MASK); + u32 misc0_color; switch (color_format) { case DP_PIXELFORMAT_YUV422: val = PIXEL_ENCODE_FORMAT_DP_ENC0_P0_YCBCR422; + misc0_color = DP_COLOR_FORMAT_YCbCr422; break; case DP_PIXELFORMAT_RGB: val = PIXEL_ENCODE_FORMAT_DP_ENC0_P0_RGB; + misc0_color = DP_COLOR_FORMAT_RGB; break; default: drm_warn(mtk_dp->drm_dev, "Unsupported color format: %d\n", @@ -479,6 +477,11 @@ static int mtk_dp_set_color_format(struct mtk_dp *mtk_dp, return -EINVAL; } + /* update MISC0 */ + mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_3034, + misc0_color, + DP_TEST_COLOR_FORMAT_MASK); + mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_303C, val, PIXEL_ENCODE_FORMAT_DP_ENC0_P0_MASK); return 0;