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[8/9] KVM: arm64: Allow control of dpISA extensions in ID_AA64ISAR3_EL1

Message ID 20241028-arm64-2024-dpisa-v1-8-a38d08b008a8@kernel.org (mailing list archive)
State New, archived
Headers show
Series arm64: Support 2024 dpISA extensions | expand

Commit Message

Mark Brown Oct. 28, 2024, 8:24 p.m. UTC
ID_AA64ISAR3_EL1 is currently marked as unallocated in KVM but does have a
number of bitfields defined in it. Expose FPRCVT and FAMINMAX, two simple
instruction only extensions to guests.

Signed-off-by: Mark Brown <broonie@kernel.org>
---
 arch/arm64/kvm/sys_regs.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

Comments

Marc Zyngier Oct. 29, 2024, 4:45 p.m. UTC | #1
On Mon, 28 Oct 2024 20:24:17 +0000,
Mark Brown <broonie@kernel.org> wrote:
> 
> ID_AA64ISAR3_EL1 is currently marked as unallocated in KVM but does have a
> number of bitfields defined in it. Expose FPRCVT and FAMINMAX, two simple
> instruction only extensions to guests.
> 
> Signed-off-by: Mark Brown <broonie@kernel.org>
> ---
>  arch/arm64/kvm/sys_regs.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
> index dad88e31f9537fe02e28b117d6a740f15572e0ba..ab348c314d7963437e1876d441169f3ef4eff095 100644
> --- a/arch/arm64/kvm/sys_regs.c
> +++ b/arch/arm64/kvm/sys_regs.c
> @@ -2409,7 +2409,8 @@ static const struct sys_reg_desc sys_reg_descs[] = {
>  	ID_WRITABLE(ID_AA64ISAR2_EL1, ~(ID_AA64ISAR2_EL1_RES0 |
>  					ID_AA64ISAR2_EL1_APA3 |
>  					ID_AA64ISAR2_EL1_GPA3)),
> -	ID_UNALLOCATED(6,3),
> +	ID_WRITABLE(ID_AA64ISAR3_EL1, (ID_AA64ISAR3_EL1_FPRCVT |
> +				       ID_AA64ISAR3_EL1_FAMINMAX)),

Please add the required sanitisation of the register so that we do not
get any surprise exposure of unhandled features when someone changes
ftr_id_aa64isar3[].

	M.
Mark Brown Oct. 29, 2024, 7:01 p.m. UTC | #2
On Tue, Oct 29, 2024 at 04:45:00PM +0000, Marc Zyngier wrote:
> Mark Brown <broonie@kernel.org> wrote:

> > +	ID_WRITABLE(ID_AA64ISAR3_EL1, (ID_AA64ISAR3_EL1_FPRCVT |
> > +				       ID_AA64ISAR3_EL1_FAMINMAX)),

> Please add the required sanitisation of the register so that we do not
> get any surprise exposure of unhandled features when someone changes
> ftr_id_aa64isar3[].

Hrm, right - sorry I missed that.  The other registers I was looking at
don't do any filtering.  This feels like something the helpers should do
but that's simply not how things are structured right now.
diff mbox series

Patch

diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
index dad88e31f9537fe02e28b117d6a740f15572e0ba..ab348c314d7963437e1876d441169f3ef4eff095 100644
--- a/arch/arm64/kvm/sys_regs.c
+++ b/arch/arm64/kvm/sys_regs.c
@@ -2409,7 +2409,8 @@  static const struct sys_reg_desc sys_reg_descs[] = {
 	ID_WRITABLE(ID_AA64ISAR2_EL1, ~(ID_AA64ISAR2_EL1_RES0 |
 					ID_AA64ISAR2_EL1_APA3 |
 					ID_AA64ISAR2_EL1_GPA3)),
-	ID_UNALLOCATED(6,3),
+	ID_WRITABLE(ID_AA64ISAR3_EL1, (ID_AA64ISAR3_EL1_FPRCVT |
+				       ID_AA64ISAR3_EL1_FAMINMAX)),
 	ID_UNALLOCATED(6,4),
 	ID_UNALLOCATED(6,5),
 	ID_UNALLOCATED(6,6),