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ARM: dts: imx6sll: Improve gpc description

Message ID 20241028124545.72652-1-festevam@gmail.com (mailing list archive)
State New
Headers show
Series ARM: dts: imx6sll: Improve gpc description | expand

Commit Message

Fabio Estevam Oct. 28, 2024, 12:45 p.m. UTC
From: Fabio Estevam <festevam@denx.de>

According to fsl,imx-gpc.yaml, 'clocks', 'clock-names', and 'pgc'
are required properties.

Describe them to fix the following dt-schema warnings:

interrupt-controller@20dc000: 'clocks' is a required property
interrupt-controller@20dc000: 'clock-names' is a required property
interrupt-controller@20dc000: 'pgc' is a required property

Signed-off-by: Fabio Estevam <festevam@denx.de>
---
 arch/arm/boot/dts/nxp/imx/imx6sll.dtsi | 12 ++++++++++++
 1 file changed, 12 insertions(+)

Comments

Shawn Guo Nov. 2, 2024, 6:55 a.m. UTC | #1
On Mon, Oct 28, 2024 at 09:45:45AM -0300, Fabio Estevam wrote:
> From: Fabio Estevam <festevam@denx.de>
> 
> According to fsl,imx-gpc.yaml, 'clocks', 'clock-names', and 'pgc'
> are required properties.
> 
> Describe them to fix the following dt-schema warnings:
> 
> interrupt-controller@20dc000: 'clocks' is a required property
> interrupt-controller@20dc000: 'clock-names' is a required property
> interrupt-controller@20dc000: 'pgc' is a required property
> 
> Signed-off-by: Fabio Estevam <festevam@denx.de>

Applied, thanks!
diff mbox series

Patch

diff --git a/arch/arm/boot/dts/nxp/imx/imx6sll.dtsi b/arch/arm/boot/dts/nxp/imx/imx6sll.dtsi
index 85fe2a4ab97a..d219c2b67294 100644
--- a/arch/arm/boot/dts/nxp/imx/imx6sll.dtsi
+++ b/arch/arm/boot/dts/nxp/imx/imx6sll.dtsi
@@ -602,6 +602,18 @@  gpc: interrupt-controller@20dc000 {
 				#interrupt-cells = <3>;
 				interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
 				interrupt-parent = <&intc>;
+				clocks = <&clks IMX6SLL_CLK_IPG>;
+				clock-names = "ipg";
+
+				pgc {
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					power-domain@0 {
+						reg = <0>;
+						#power-domain-cells = <0>;
+					};
+				};
 			};
 
 			iomuxc: pinctrl@20e0000 {