| Message ID | 20241029-pci_fixup_addr-v7-2-8310dc24fb7c@nxp.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | PCI: dwc: opitimaze RC Host/EP pci_fixup_addr() | expand |
On Tue, Oct 29, 2024 at 12:36:35PM -0400, Frank Li wrote: Please reword the subject as: PCI: dwc: Use devicetree 'ranges' property to get rid of cpu_addr_fixup() callback > parent_bus_addr in struct of_range can indicate address information just > ahead of PCIe controller. Most system's bus fabric use 1:1 map between > input and output address. but some hardware like i.MX8QXP doesn't use 1:1 > map. See below diagram: > > ┌─────────┐ ┌────────────┐ > ┌─────┐ │ │ IA: 0x8ff8_0000 │ │ > │ CPU ├───►│ ┌────►├─────────────────┐ │ PCI │ > └─────┘ │ │ │ IA: 0x8ff0_0000 │ │ │ > CPU Addr │ │ ┌─►├─────────────┐ │ │ Controller │ > 0x7ff8_0000─┼───┘ │ │ │ │ │ │ > │ │ │ │ │ │ │ PCI Addr > 0x7ff0_0000─┼──────┘ │ │ └──► IOSpace ─┼────────────► > │ │ │ │ │ 0 > 0x7000_0000─┼────────►├─────────┐ │ │ │ > └─────────┘ │ └──────► CfgSpace ─┼────────────► > BUS Fabric │ │ │ 0 > │ │ │ > └──────────► MemSpace ─┼────────────► > IA: 0x8000_0000 │ │ 0x8000_0000 > └────────────┘ > > bus@5f000000 { > compatible = "simple-bus"; > #address-cells = <1>; > #size-cells = <1>; > ranges = <0x80000000 0x0 0x70000000 0x10000000>; > > pcie@5f010000 { > compatible = "fsl,imx8q-pcie"; > reg = <0x5f010000 0x10000>, <0x8ff00000 0x80000>; > reg-names = "dbi", "config"; > #address-cells = <3>; > #size-cells = <2>; > device_type = "pci"; > bus-range = <0x00 0xff>; > ranges = <0x81000000 0 0x00000000 0x8ff80000 0 0x00010000>, > <0x82000000 0 0x80000000 0x80000000 0 0x0ff00000>; > ... > }; > }; > > Term internal address (IA) here means the address just before PCIe > controller. After ATU use this IA instead CPU address, cpu_addr_fixup() can > be removed. > > Signed-off-by: Frank Li <Frank.Li@nxp.com> > --- > Add a resource_size_t parent_bus_addr local varible to fix 32bit build > error. > | Reported-by: kernel test robot <lkp@intel.com> > | Closes: https://lore.kernel.org/oe-kbuild-all/202410291546.kvgEWJv7-lkp@intel.com/ > > Chagne from v5 to v6 > -add comments for of_property_read_reg(). > > Change from v4 to v5 > - remove confused 0x5f00_0000 range in sample dts. > - reorder address at above diagram. > > Change from v3 to v4 > - none > > Change from v2 to v3 > - %s/cpu_untranslate_addr/parent_bus_addr/g > - update diagram. > - improve commit message. > > Change from v1 to v2 > - update because patch1 change get untranslate address method. > - add using_dtbus_info in case break back compatibility for exited platform. > --- > drivers/pci/controller/dwc/pcie-designware-host.c | 55 ++++++++++++++++++++++- > drivers/pci/controller/dwc/pcie-designware.h | 8 ++++ > 2 files changed, 62 insertions(+), 1 deletion(-) > > diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c > index 3e41865c72904..ea01b7bda0a76 100644 > --- a/drivers/pci/controller/dwc/pcie-designware-host.c > +++ b/drivers/pci/controller/dwc/pcie-designware-host.c > @@ -418,6 +418,34 @@ static void dw_pcie_host_request_msg_tlp_res(struct dw_pcie_rp *pp) > } > } > > +static int dw_pcie_get_untranslate_addr(struct dw_pcie *pci, resource_size_t pci_addr, > + resource_size_t *i_addr) dw_pcie_get_parent_addr()? Since this function is anyway reading the parent address from DT. > +{ > + struct device *dev = pci->dev; > + struct device_node *np = dev->of_node; > + struct of_range_parser parser; > + struct of_range range; > + int ret; > + > + if (!pci->using_dtbus_info) { > + *i_addr = pci_addr; > + return 0; > + } > + > + ret = of_range_parser_init(&parser, np); > + if (ret) > + return ret; > + > + for_each_of_pci_range(&parser, &range) { > + if (pci_addr == range.bus_addr) { > + *i_addr = range.parent_bus_addr; > + break; > + } > + } > + > + return 0; > +} > + > int dw_pcie_host_init(struct dw_pcie_rp *pp) > { > struct dw_pcie *pci = to_dw_pcie_from_pp(pp); > @@ -427,6 +455,7 @@ int dw_pcie_host_init(struct dw_pcie_rp *pp) > struct resource_entry *win; > struct pci_host_bridge *bridge; > struct resource *res; > + int index; > int ret; > > raw_spin_lock_init(&pp->lock); > @@ -440,6 +469,20 @@ int dw_pcie_host_init(struct dw_pcie_rp *pp) > pp->cfg0_size = resource_size(res); > pp->cfg0_base = res->start; > > + if (pci->using_dtbus_info) { > + index = of_property_match_string(np, "reg-names", "config"); > + if (index < 0) > + return -EINVAL; > + /* > + * Retrieve the parent bus address of PCI config space. > + * If the parent bus ranges in the device tree provide > + * the correct address conversion information, set > + * 'using_dtbus_info' to true, The 'cpu_addr_fixup()' > + * can be eliminated. > + */ Nobody will switch to 'ranges' property if you mention it in comments. We usually add dev_warn_once() to print a warning for broken DT so that the users will try to fix it. You can use below diff (as a separate patch ofc): ``` diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c index 6d6cbc8b5b2c..d1e5395386fe 100644 --- a/drivers/pci/controller/dwc/pcie-designware.c +++ b/drivers/pci/controller/dwc/pcie-designware.c @@ -844,6 +844,9 @@ void dw_pcie_iatu_detect(struct dw_pcie *pci) dw_pcie_cap_is(pci, IATU_UNROLL) ? "T" : "F", pci->num_ob_windows, pci->num_ib_windows, pci->region_align / SZ_1K, (pci->region_limit + 1) / SZ_1G); + + if (pci->ops && pci->ops->cpu_addr_fixup) + dev_warn_once(pci->dev, "Broken \"ranges\" property detected. Please fix DT!\n"); } static u32 dw_pcie_readl_dma(struct dw_pcie *pci, u32 reg) ``` > + of_property_read_reg(np, index, &pp->cfg0_base, NULL); Can you explain what is going on here? > + } > + > pp->va_cfg0_base = devm_pci_remap_cfg_resource(dev, res); > if (IS_ERR(pp->va_cfg0_base)) > return PTR_ERR(pp->va_cfg0_base); > @@ -462,6 +505,9 @@ int dw_pcie_host_init(struct dw_pcie_rp *pp) > pp->io_base = pci_pio_to_address(win->res->start); > } > > + if (dw_pcie_get_untranslate_addr(pci, pp->io_bus_addr, &pp->io_base)) > + return -ENODEV; Use actual return value here and below. > + > /* Set default bus ops */ > bridge->ops = &dw_pcie_ops; > bridge->child_ops = &dw_child_pcie_ops; > @@ -722,6 +768,8 @@ static int dw_pcie_iatu_setup(struct dw_pcie_rp *pp) > > i = 0; > resource_list_for_each_entry(entry, &pp->bridge->windows) { > + resource_size_t parent_bus_addr; > + > if (resource_type(entry->res) != IORESOURCE_MEM) > continue; > > @@ -730,9 +778,14 @@ static int dw_pcie_iatu_setup(struct dw_pcie_rp *pp) > > atu.index = i; > atu.type = PCIE_ATU_TYPE_MEM; > - atu.cpu_addr = entry->res->start; > + parent_bus_addr = entry->res->start; > atu.pci_addr = entry->res->start - entry->offset; > > + if (dw_pcie_get_untranslate_addr(pci, entry->res->start, &parent_bus_addr)) > + return -EINVAL; > + > + atu.cpu_addr = parent_bus_addr; > + > /* Adjust iATU size if MSG TLP region was allocated before */ > if (pp->msg_res && pp->msg_res->parent == entry->res) > atu.size = resource_size(entry->res) - > diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h > index 347ab74ac35aa..f8067393ad35a 100644 > --- a/drivers/pci/controller/dwc/pcie-designware.h > +++ b/drivers/pci/controller/dwc/pcie-designware.h > @@ -463,6 +463,14 @@ struct dw_pcie { > struct reset_control_bulk_data core_rsts[DW_PCIE_NUM_CORE_RSTS]; > struct gpio_desc *pe_rst; > bool suspended; > + /* > + * Use device tree 'ranges' property of bus node instead using > + * cpu_addr_fixup(). Some old platform dts 'ranges' in bus node may not > + * reflect real hardware's behavior. In case break these platform back > + * compatibility, add below flags. Set it true if dts already correct > + * indicate bus fabric address convert. /* * This flag indicates that the vendor driver uses devicetree 'ranges' * property to allow iATU to use the Intermediate Address (IA) for * outbound mapping. Using this flag also avoids the usage of * 'cpu_addr_fixup' callback implementation in the driver. */ > + */ > + bool using_dtbus_info; 'use_dt_ranges'? - Mani
On Fri, Nov 15, 2024 at 11:21:48PM +0530, Manivannan Sadhasivam wrote: > On Tue, Oct 29, 2024 at 12:36:35PM -0400, Frank Li wrote: > > Please reword the subject as: > > PCI: dwc: Use devicetree 'ranges' property to get rid of cpu_addr_fixup() callback > > > parent_bus_addr in struct of_range can indicate address information just > > ahead of PCIe controller. Most system's bus fabric use 1:1 map between > > input and output address. but some hardware like i.MX8QXP doesn't use 1:1 > > map. See below diagram: > > > > ┌─────────┐ ┌────────────┐ > > ┌─────┐ │ │ IA: 0x8ff8_0000 │ │ > > │ CPU ├───►│ ┌────►├─────────────────┐ │ PCI │ > > └─────┘ │ │ │ IA: 0x8ff0_0000 │ │ │ > > CPU Addr │ │ ┌─►├─────────────┐ │ │ Controller │ > > 0x7ff8_0000─┼───┘ │ │ │ │ │ │ > > │ │ │ │ │ │ │ PCI Addr > > 0x7ff0_0000─┼──────┘ │ │ └──► IOSpace ─┼────────────► > > │ │ │ │ │ 0 > > 0x7000_0000─┼────────►├─────────┐ │ │ │ > > └─────────┘ │ └──────► CfgSpace ─┼────────────► > > BUS Fabric │ │ │ 0 > > │ │ │ > > └──────────► MemSpace ─┼────────────► > > IA: 0x8000_0000 │ │ 0x8000_0000 > > └────────────┘ > > > > bus@5f000000 { > > compatible = "simple-bus"; > > #address-cells = <1>; > > #size-cells = <1>; > > ranges = <0x80000000 0x0 0x70000000 0x10000000>; > > > > pcie@5f010000 { > > compatible = "fsl,imx8q-pcie"; > > reg = <0x5f010000 0x10000>, <0x8ff00000 0x80000>; > > reg-names = "dbi", "config"; > > #address-cells = <3>; > > #size-cells = <2>; > > device_type = "pci"; > > bus-range = <0x00 0xff>; > > ranges = <0x81000000 0 0x00000000 0x8ff80000 0 0x00010000>, > > <0x82000000 0 0x80000000 0x80000000 0 0x0ff00000>; > > ... > > }; > > }; > > > > Term internal address (IA) here means the address just before PCIe > > controller. After ATU use this IA instead CPU address, cpu_addr_fixup() can > > be removed. > > > > Signed-off-by: Frank Li <Frank.Li@nxp.com> > > --- > > Add a resource_size_t parent_bus_addr local varible to fix 32bit build > > error. > > | Reported-by: kernel test robot <lkp@intel.com> > > | Closes: https://lore.kernel.org/oe-kbuild-all/202410291546.kvgEWJv7-lkp@intel.com/ > > > > Chagne from v5 to v6 > > -add comments for of_property_read_reg(). > > > > Change from v4 to v5 > > - remove confused 0x5f00_0000 range in sample dts. > > - reorder address at above diagram. > > > > Change from v3 to v4 > > - none > > > > Change from v2 to v3 > > - %s/cpu_untranslate_addr/parent_bus_addr/g > > - update diagram. > > - improve commit message. > > > > Change from v1 to v2 > > - update because patch1 change get untranslate address method. > > - add using_dtbus_info in case break back compatibility for exited platform. > > --- > > drivers/pci/controller/dwc/pcie-designware-host.c | 55 ++++++++++++++++++++++- > > drivers/pci/controller/dwc/pcie-designware.h | 8 ++++ > > 2 files changed, 62 insertions(+), 1 deletion(-) > > > > diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c > > index 3e41865c72904..ea01b7bda0a76 100644 > > --- a/drivers/pci/controller/dwc/pcie-designware-host.c > > +++ b/drivers/pci/controller/dwc/pcie-designware-host.c > > @@ -418,6 +418,34 @@ static void dw_pcie_host_request_msg_tlp_res(struct dw_pcie_rp *pp) > > } > > } > > > > +static int dw_pcie_get_untranslate_addr(struct dw_pcie *pci, resource_size_t pci_addr, > > + resource_size_t *i_addr) > > dw_pcie_get_parent_addr()? Since this function is anyway reading the parent > address from DT. > > > +{ > > + struct device *dev = pci->dev; > > + struct device_node *np = dev->of_node; > > + struct of_range_parser parser; > > + struct of_range range; > > + int ret; > > + > > + if (!pci->using_dtbus_info) { > > + *i_addr = pci_addr; > > + return 0; > > + } > > + > > + ret = of_range_parser_init(&parser, np); > > + if (ret) > > + return ret; > > + > > + for_each_of_pci_range(&parser, &range) { > > + if (pci_addr == range.bus_addr) { > > + *i_addr = range.parent_bus_addr; > > + break; > > + } > > + } > > + > > + return 0; > > +} > > + > > int dw_pcie_host_init(struct dw_pcie_rp *pp) > > { > > struct dw_pcie *pci = to_dw_pcie_from_pp(pp); > > @@ -427,6 +455,7 @@ int dw_pcie_host_init(struct dw_pcie_rp *pp) > > struct resource_entry *win; > > struct pci_host_bridge *bridge; > > struct resource *res; > > + int index; > > int ret; > > > > raw_spin_lock_init(&pp->lock); > > @@ -440,6 +469,20 @@ int dw_pcie_host_init(struct dw_pcie_rp *pp) > > pp->cfg0_size = resource_size(res); > > pp->cfg0_base = res->start; > > > > + if (pci->using_dtbus_info) { > > + index = of_property_match_string(np, "reg-names", "config"); > > + if (index < 0) > > + return -EINVAL; > > + /* > > + * Retrieve the parent bus address of PCI config space. > > + * If the parent bus ranges in the device tree provide > > + * the correct address conversion information, set > > + * 'using_dtbus_info' to true, The 'cpu_addr_fixup()' > > + * can be eliminated. > > + */ > > Nobody will switch to 'ranges' property if you mention it in comments. We > usually add dev_warn_once() to print a warning for broken DT so that the users > will try to fix it. You can use below diff (as a separate patch ofc): > > ``` > diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c > index 6d6cbc8b5b2c..d1e5395386fe 100644 > --- a/drivers/pci/controller/dwc/pcie-designware.c > +++ b/drivers/pci/controller/dwc/pcie-designware.c > @@ -844,6 +844,9 @@ void dw_pcie_iatu_detect(struct dw_pcie *pci) > dw_pcie_cap_is(pci, IATU_UNROLL) ? "T" : "F", > pci->num_ob_windows, pci->num_ib_windows, > pci->region_align / SZ_1K, (pci->region_limit + 1) / SZ_1G); > + > + if (pci->ops && pci->ops->cpu_addr_fixup) > + dev_warn_once(pci->dev, "Broken \"ranges\" property detected. Please fix DT!\n"); How about "Detect use old method "cpu_addr_fixup()", it should correct DT's 'ranges' and remove cpu_addr_fixup()? > } > > static u32 dw_pcie_readl_dma(struct dw_pcie *pci, u32 reg) > ``` > > > + of_property_read_reg(np, index, &pp->cfg0_base, NULL); > > Can you explain what is going on here? Because dwc use reg-name 'config' to get config space, of_property_read_reg() will get untranslate address 'parent' bus address. <0x8ff00000 0x80000> at example address. cfg0_base is used to set outbound ATU. > > > + } > > + > > pp->va_cfg0_base = devm_pci_remap_cfg_resource(dev, res); > > if (IS_ERR(pp->va_cfg0_base)) > > return PTR_ERR(pp->va_cfg0_base); > > @@ -462,6 +505,9 @@ int dw_pcie_host_init(struct dw_pcie_rp *pp) > > pp->io_base = pci_pio_to_address(win->res->start); > > } > > > > + if (dw_pcie_get_untranslate_addr(pci, pp->io_bus_addr, &pp->io_base)) > > + return -ENODEV; > > Use actual return value here and below. > > > + > > /* Set default bus ops */ > > bridge->ops = &dw_pcie_ops; > > bridge->child_ops = &dw_child_pcie_ops; > > @@ -722,6 +768,8 @@ static int dw_pcie_iatu_setup(struct dw_pcie_rp *pp) > > > > i = 0; > > resource_list_for_each_entry(entry, &pp->bridge->windows) { > > + resource_size_t parent_bus_addr; > > + > > if (resource_type(entry->res) != IORESOURCE_MEM) > > continue; > > > > @@ -730,9 +778,14 @@ static int dw_pcie_iatu_setup(struct dw_pcie_rp *pp) > > > > atu.index = i; > > atu.type = PCIE_ATU_TYPE_MEM; > > - atu.cpu_addr = entry->res->start; > > + parent_bus_addr = entry->res->start; > > atu.pci_addr = entry->res->start - entry->offset; > > > > + if (dw_pcie_get_untranslate_addr(pci, entry->res->start, &parent_bus_addr)) > > + return -EINVAL; > > + > > + atu.cpu_addr = parent_bus_addr; > > + > > /* Adjust iATU size if MSG TLP region was allocated before */ > > if (pp->msg_res && pp->msg_res->parent == entry->res) > > atu.size = resource_size(entry->res) - > > diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h > > index 347ab74ac35aa..f8067393ad35a 100644 > > --- a/drivers/pci/controller/dwc/pcie-designware.h > > +++ b/drivers/pci/controller/dwc/pcie-designware.h > > @@ -463,6 +463,14 @@ struct dw_pcie { > > struct reset_control_bulk_data core_rsts[DW_PCIE_NUM_CORE_RSTS]; > > struct gpio_desc *pe_rst; > > bool suspended; > > + /* > > + * Use device tree 'ranges' property of bus node instead using > > + * cpu_addr_fixup(). Some old platform dts 'ranges' in bus node may not > > + * reflect real hardware's behavior. In case break these platform back > > + * compatibility, add below flags. Set it true if dts already correct > > + * indicate bus fabric address convert. > > /* > * This flag indicates that the vendor driver uses devicetree 'ranges' > * property to allow iATU to use the Intermediate Address (IA) for > * outbound mapping. Using this flag also avoids the usage of > * 'cpu_addr_fixup' callback implementation in the driver. > */ > > > + */ > > + bool using_dtbus_info; > > 'use_dt_ranges'? It will be confused because pcie node alreadys use ranges, just parent bus 's ranges is wrong. 'use_dtbus_ranges' ? Frank > > - Mani > > -- > மணிவண்ணன் சதாசிவம்
On Fri, Nov 15, 2024 at 02:18:38PM -0500, Frank Li wrote: [...] > > > + if (pci->using_dtbus_info) { > > > + index = of_property_match_string(np, "reg-names", "config"); > > > + if (index < 0) > > > + return -EINVAL; > > > + /* > > > + * Retrieve the parent bus address of PCI config space. > > > + * If the parent bus ranges in the device tree provide > > > + * the correct address conversion information, set > > > + * 'using_dtbus_info' to true, The 'cpu_addr_fixup()' > > > + * can be eliminated. > > > + */ > > > > Nobody will switch to 'ranges' property if you mention it in comments. We > > usually add dev_warn_once() to print a warning for broken DT so that the users > > will try to fix it. You can use below diff (as a separate patch ofc): > > > > ``` > > diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c > > index 6d6cbc8b5b2c..d1e5395386fe 100644 > > --- a/drivers/pci/controller/dwc/pcie-designware.c > > +++ b/drivers/pci/controller/dwc/pcie-designware.c > > @@ -844,6 +844,9 @@ void dw_pcie_iatu_detect(struct dw_pcie *pci) > > dw_pcie_cap_is(pci, IATU_UNROLL) ? "T" : "F", > > pci->num_ob_windows, pci->num_ib_windows, > > pci->region_align / SZ_1K, (pci->region_limit + 1) / SZ_1G); > > + > > + if (pci->ops && pci->ops->cpu_addr_fixup) > > + dev_warn_once(pci->dev, "Broken \"ranges\" property detected. Please fix DT!\n"); > > How about "Detect use old method "cpu_addr_fixup()", it should correct DT's > 'ranges' and remove cpu_addr_fixup()? > Hmm, yeah makes sense: /* * If the parent 'ranges' property in DT correctly describes the address * translation, cpu_addr_fixup() callback is not needed. */ dev_warn_once(pci->dev, "cpu_addr_fixup() usage detected. Please fix DT!\n"; But then the drivers need to be smart enough to detect the valid parent 'ranges' property and then only use the callback. Because, callback has to be present to support older DTs. > > } > > > > static u32 dw_pcie_readl_dma(struct dw_pcie *pci, u32 reg) > > ``` > > > > > + of_property_read_reg(np, index, &pp->cfg0_base, NULL); > > > > Can you explain what is going on here? > > Because dwc use reg-name 'config' to get config space, > of_property_read_reg() will get untranslate address 'parent' bus address. > <0x8ff00000 0x80000> at example address. > > cfg0_base is used to set outbound ATU. > Ok, please add a comment like this: /* Get the untranslated 'config' address */ Same for other usage of of_property_read_reg(). > > > > > + } > > > + > > > pp->va_cfg0_base = devm_pci_remap_cfg_resource(dev, res); > > > if (IS_ERR(pp->va_cfg0_base)) > > > return PTR_ERR(pp->va_cfg0_base); > > > @@ -462,6 +505,9 @@ int dw_pcie_host_init(struct dw_pcie_rp *pp) > > > pp->io_base = pci_pio_to_address(win->res->start); > > > } > > > > > > + if (dw_pcie_get_untranslate_addr(pci, pp->io_bus_addr, &pp->io_base)) > > > + return -ENODEV; > > > > Use actual return value here and below. > > > > > + > > > /* Set default bus ops */ > > > bridge->ops = &dw_pcie_ops; > > > bridge->child_ops = &dw_child_pcie_ops; > > > @@ -722,6 +768,8 @@ static int dw_pcie_iatu_setup(struct dw_pcie_rp *pp) > > > > > > i = 0; > > > resource_list_for_each_entry(entry, &pp->bridge->windows) { > > > + resource_size_t parent_bus_addr; > > > + > > > if (resource_type(entry->res) != IORESOURCE_MEM) > > > continue; > > > > > > @@ -730,9 +778,14 @@ static int dw_pcie_iatu_setup(struct dw_pcie_rp *pp) > > > > > > atu.index = i; > > > atu.type = PCIE_ATU_TYPE_MEM; > > > - atu.cpu_addr = entry->res->start; > > > + parent_bus_addr = entry->res->start; > > > atu.pci_addr = entry->res->start - entry->offset; > > > > > > + if (dw_pcie_get_untranslate_addr(pci, entry->res->start, &parent_bus_addr)) > > > + return -EINVAL; > > > + > > > + atu.cpu_addr = parent_bus_addr; > > > + > > > /* Adjust iATU size if MSG TLP region was allocated before */ > > > if (pp->msg_res && pp->msg_res->parent == entry->res) > > > atu.size = resource_size(entry->res) - > > > diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h > > > index 347ab74ac35aa..f8067393ad35a 100644 > > > --- a/drivers/pci/controller/dwc/pcie-designware.h > > > +++ b/drivers/pci/controller/dwc/pcie-designware.h > > > @@ -463,6 +463,14 @@ struct dw_pcie { > > > struct reset_control_bulk_data core_rsts[DW_PCIE_NUM_CORE_RSTS]; > > > struct gpio_desc *pe_rst; > > > bool suspended; > > > + /* > > > + * Use device tree 'ranges' property of bus node instead using > > > + * cpu_addr_fixup(). Some old platform dts 'ranges' in bus node may not > > > + * reflect real hardware's behavior. In case break these platform back > > > + * compatibility, add below flags. Set it true if dts already correct > > > + * indicate bus fabric address convert. > > > > /* > > * This flag indicates that the vendor driver uses devicetree 'ranges' > > * property to allow iATU to use the Intermediate Address (IA) for > > * outbound mapping. Using this flag also avoids the usage of > > * 'cpu_addr_fixup' callback implementation in the driver. > > */ > > > > > + */ > > > + bool using_dtbus_info; > > > > 'use_dt_ranges'? > > It will be confused because pcie node alreadys use ranges, just parent bus > 's ranges is wrong. > > 'use_dtbus_ranges' ? > There is nothing called 'dtbus'. How about, "use_parent_dt_ranges"? - Mani
diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c index 3e41865c72904..ea01b7bda0a76 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -418,6 +418,34 @@ static void dw_pcie_host_request_msg_tlp_res(struct dw_pcie_rp *pp) } } +static int dw_pcie_get_untranslate_addr(struct dw_pcie *pci, resource_size_t pci_addr, + resource_size_t *i_addr) +{ + struct device *dev = pci->dev; + struct device_node *np = dev->of_node; + struct of_range_parser parser; + struct of_range range; + int ret; + + if (!pci->using_dtbus_info) { + *i_addr = pci_addr; + return 0; + } + + ret = of_range_parser_init(&parser, np); + if (ret) + return ret; + + for_each_of_pci_range(&parser, &range) { + if (pci_addr == range.bus_addr) { + *i_addr = range.parent_bus_addr; + break; + } + } + + return 0; +} + int dw_pcie_host_init(struct dw_pcie_rp *pp) { struct dw_pcie *pci = to_dw_pcie_from_pp(pp); @@ -427,6 +455,7 @@ int dw_pcie_host_init(struct dw_pcie_rp *pp) struct resource_entry *win; struct pci_host_bridge *bridge; struct resource *res; + int index; int ret; raw_spin_lock_init(&pp->lock); @@ -440,6 +469,20 @@ int dw_pcie_host_init(struct dw_pcie_rp *pp) pp->cfg0_size = resource_size(res); pp->cfg0_base = res->start; + if (pci->using_dtbus_info) { + index = of_property_match_string(np, "reg-names", "config"); + if (index < 0) + return -EINVAL; + /* + * Retrieve the parent bus address of PCI config space. + * If the parent bus ranges in the device tree provide + * the correct address conversion information, set + * 'using_dtbus_info' to true, The 'cpu_addr_fixup()' + * can be eliminated. + */ + of_property_read_reg(np, index, &pp->cfg0_base, NULL); + } + pp->va_cfg0_base = devm_pci_remap_cfg_resource(dev, res); if (IS_ERR(pp->va_cfg0_base)) return PTR_ERR(pp->va_cfg0_base); @@ -462,6 +505,9 @@ int dw_pcie_host_init(struct dw_pcie_rp *pp) pp->io_base = pci_pio_to_address(win->res->start); } + if (dw_pcie_get_untranslate_addr(pci, pp->io_bus_addr, &pp->io_base)) + return -ENODEV; + /* Set default bus ops */ bridge->ops = &dw_pcie_ops; bridge->child_ops = &dw_child_pcie_ops; @@ -722,6 +768,8 @@ static int dw_pcie_iatu_setup(struct dw_pcie_rp *pp) i = 0; resource_list_for_each_entry(entry, &pp->bridge->windows) { + resource_size_t parent_bus_addr; + if (resource_type(entry->res) != IORESOURCE_MEM) continue; @@ -730,9 +778,14 @@ static int dw_pcie_iatu_setup(struct dw_pcie_rp *pp) atu.index = i; atu.type = PCIE_ATU_TYPE_MEM; - atu.cpu_addr = entry->res->start; + parent_bus_addr = entry->res->start; atu.pci_addr = entry->res->start - entry->offset; + if (dw_pcie_get_untranslate_addr(pci, entry->res->start, &parent_bus_addr)) + return -EINVAL; + + atu.cpu_addr = parent_bus_addr; + /* Adjust iATU size if MSG TLP region was allocated before */ if (pp->msg_res && pp->msg_res->parent == entry->res) atu.size = resource_size(entry->res) - diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h index 347ab74ac35aa..f8067393ad35a 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -463,6 +463,14 @@ struct dw_pcie { struct reset_control_bulk_data core_rsts[DW_PCIE_NUM_CORE_RSTS]; struct gpio_desc *pe_rst; bool suspended; + /* + * Use device tree 'ranges' property of bus node instead using + * cpu_addr_fixup(). Some old platform dts 'ranges' in bus node may not + * reflect real hardware's behavior. In case break these platform back + * compatibility, add below flags. Set it true if dts already correct + * indicate bus fabric address convert. + */ + bool using_dtbus_info; }; #define to_dw_pcie_from_pp(port) container_of((port), struct dw_pcie, pp)
parent_bus_addr in struct of_range can indicate address information just ahead of PCIe controller. Most system's bus fabric use 1:1 map between input and output address. but some hardware like i.MX8QXP doesn't use 1:1 map. See below diagram: ┌─────────┐ ┌────────────┐ ┌─────┐ │ │ IA: 0x8ff8_0000 │ │ │ CPU ├───►│ ┌────►├─────────────────┐ │ PCI │ └─────┘ │ │ │ IA: 0x8ff0_0000 │ │ │ CPU Addr │ │ ┌─►├─────────────┐ │ │ Controller │ 0x7ff8_0000─┼───┘ │ │ │ │ │ │ │ │ │ │ │ │ │ PCI Addr 0x7ff0_0000─┼──────┘ │ │ └──► IOSpace ─┼────────────► │ │ │ │ │ 0 0x7000_0000─┼────────►├─────────┐ │ │ │ └─────────┘ │ └──────► CfgSpace ─┼────────────► BUS Fabric │ │ │ 0 │ │ │ └──────────► MemSpace ─┼────────────► IA: 0x8000_0000 │ │ 0x8000_0000 └────────────┘ bus@5f000000 { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges = <0x80000000 0x0 0x70000000 0x10000000>; pcie@5f010000 { compatible = "fsl,imx8q-pcie"; reg = <0x5f010000 0x10000>, <0x8ff00000 0x80000>; reg-names = "dbi", "config"; #address-cells = <3>; #size-cells = <2>; device_type = "pci"; bus-range = <0x00 0xff>; ranges = <0x81000000 0 0x00000000 0x8ff80000 0 0x00010000>, <0x82000000 0 0x80000000 0x80000000 0 0x0ff00000>; ... }; }; Term internal address (IA) here means the address just before PCIe controller. After ATU use this IA instead CPU address, cpu_addr_fixup() can be removed. Signed-off-by: Frank Li <Frank.Li@nxp.com> --- Add a resource_size_t parent_bus_addr local varible to fix 32bit build error. | Reported-by: kernel test robot <lkp@intel.com> | Closes: https://lore.kernel.org/oe-kbuild-all/202410291546.kvgEWJv7-lkp@intel.com/ Chagne from v5 to v6 -add comments for of_property_read_reg(). Change from v4 to v5 - remove confused 0x5f00_0000 range in sample dts. - reorder address at above diagram. Change from v3 to v4 - none Change from v2 to v3 - %s/cpu_untranslate_addr/parent_bus_addr/g - update diagram. - improve commit message. Change from v1 to v2 - update because patch1 change get untranslate address method. - add using_dtbus_info in case break back compatibility for exited platform. --- drivers/pci/controller/dwc/pcie-designware-host.c | 55 ++++++++++++++++++++++- drivers/pci/controller/dwc/pcie-designware.h | 8 ++++ 2 files changed, 62 insertions(+), 1 deletion(-)