Message ID | 20241030110120.332802-2-claudiu.beznea.uj@bp.renesas.com (mailing list archive) |
---|---|
State | New |
Headers | show |
Series | Add RTC support for the Renesas RZ/G3S SoC | expand |
On Wed, Oct 30, 2024 at 01:01:11PM +0200, Claudiu wrote: > From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> > > The VBATTB IP of the Renesas RZ/G3S SoC controls the clock for RTC, > the tamper detector and a small general usage memory of 128B. > > The VBATTB controller controls the clock for the RTC on the Renesas > RZ/G3S. The HW block diagram for the clock logic is as follows: > > +----------+ XC `\ > RTXIN --->| |----->| \ +----+ VBATTCLK > | 32K clock| | |----->|gate|-----------> > | osc | XBYP | | +----+ > RTXOUT --->| |----->| / > +----------+ ,/ > > One could connect as input to this HW block either a crystal or > an external clock device. This is board specific. > > After discussions w/ Stephen Boyd the clock tree associated with this > hardware block was exported in Linux as: > > input-xtal > xbyp > xc > mux > vbattclk > > where: > - input-xtal is the input clock (connected to RTXIN, RTXOUT pins) > - xc, xbyp are mux inputs > - mux is the internal mux > - vbattclk is the gate clock that feeds in the end the RTC > > to allow selecting the input of the MUX though assigned-clock DT > properties, using the already existing clock drivers and avoid adding > other DT properties. > > This allows select the input of the mux based on the type of the > connected input clock: > - if the 32768 crystal is connected as input for the VBATTB, > the input of the mux should be xc > - if an external clock device is connected as input for the VBATTB the > input of the mux should be xbyp > > Add bindings for the VBATTB controller. > > Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> > Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> > --- > > Changes in v5: > - used spaces in the diagram from the patch description > - added "This is board specific" in the board description to emphasize > the usage of the assigned-clocks in the example > - added default for quartz-load-femtofarads > - collected tags Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Best regards, Krzysztof
diff --git a/Documentation/devicetree/bindings/clock/renesas,r9a08g045-vbattb.yaml b/Documentation/devicetree/bindings/clock/renesas,r9a08g045-vbattb.yaml new file mode 100644 index 000000000000..3707e4118949 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/renesas,r9a08g045-vbattb.yaml @@ -0,0 +1,84 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/renesas,r9a08g045-vbattb.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas Battery Backup Function (VBATTB) + +description: + Renesas VBATTB is an always on powered module (backed by battery) which + controls the RTC clock (VBATTCLK), tamper detection logic and a small + general usage memory (128B). + +maintainers: + - Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> + +properties: + compatible: + const: renesas,r9a08g045-vbattb + + reg: + maxItems: 1 + + interrupts: + items: + - description: tamper detector interrupt + + clocks: + items: + - description: VBATTB module clock + - description: RTC input clock (crystal or external clock device) + + clock-names: + items: + - const: bclk + - const: rtx + + '#clock-cells': + const: 1 + + power-domains: + maxItems: 1 + + resets: + items: + - description: VBATTB module reset + + quartz-load-femtofarads: + description: load capacitance of the on board crystal + enum: [ 4000, 7000, 9000, 12500 ] + default: 4000 + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - '#clock-cells' + - power-domains + - resets + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/r9a08g045-cpg.h> + #include <dt-bindings/clock/renesas,r9a08g045-vbattb.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/interrupt-controller/irq.h> + + clock-controller@1005c000 { + compatible = "renesas,r9a08g045-vbattb"; + reg = <0x1005c000 0x1000>; + interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD R9A08G045_VBAT_BCLK>, <&vbattb_xtal>; + clock-names = "bclk", "rtx"; + assigned-clocks = <&vbattb VBATTB_MUX>; + assigned-clock-parents = <&vbattb VBATTB_XC>; + #clock-cells = <1>; + power-domains = <&cpg>; + resets = <&cpg R9A08G045_VBAT_BRESETN>; + quartz-load-femtofarads = <12500>; + }; diff --git a/include/dt-bindings/clock/renesas,r9a08g045-vbattb.h b/include/dt-bindings/clock/renesas,r9a08g045-vbattb.h new file mode 100644 index 000000000000..67774eafad06 --- /dev/null +++ b/include/dt-bindings/clock/renesas,r9a08g045-vbattb.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) + * + * Copyright (C) 2024 Renesas Electronics Corp. + */ +#ifndef __DT_BINDINGS_CLOCK_R9A08G045_VBATTB_H__ +#define __DT_BINDINGS_CLOCK_R9A08G045_VBATTB_H__ + +#define VBATTB_XC 0 +#define VBATTB_XBYP 1 +#define VBATTB_MUX 2 +#define VBATTB_VBATTCLK 3 + +#endif /* __DT_BINDINGS_CLOCK_R9A08G045_VBATTB_H__ */