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Wysocki" , Lee Jones , Shawn Guo , Sascha Hauer , Fabio Estevam , Dong Aisheng , Jacky Bai Cc: linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, NXP S32 Linux Team , Christophe Lizzi , Alberto Ruiz , Enric Balletbo , Pengutronix Kernel Team , imx@lists.linux.dev Subject: [PATCH v5 3/7] arm64: dts: s32g: make pinctrl part of mfd node Date: Fri, 1 Nov 2024 10:06:09 +0200 Message-ID: <20241101080614.1070819-4-andrei.stefanescu@oss.nxp.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241101080614.1070819-1-andrei.stefanescu@oss.nxp.com> References: <20241101080614.1070819-1-andrei.stefanescu@oss.nxp.com> X-ClientProxiedBy: AM0PR10CA0115.EURPRD10.PROD.OUTLOOK.COM (2603:10a6:208:e6::32) To AM9PR04MB8487.eurprd04.prod.outlook.com (2603:10a6:20b:41a::6) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: AM9PR04MB8487:EE_|PR3PR04MB7225:EE_ X-MS-Office365-Filtering-Correlation-Id: e964c3be-bdf6-4a4a-6764-08dcfa4c21f6 X-MS-Exchange-SharedMailbox-RoutingAgent-Processed: True X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|52116014|7416014|366016|376014|921020|38350700014; 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Therefore, the old pinctrl node is deprecated. Move the pinctrl related properties inside the new "nxp-siul2" node. The latter one is now used to represent the mfd device. Signed-off-by: Andrei Stefanescu --- arch/arm64/boot/dts/freescale/s32g2.dtsi | 26 +++++++++++------------- arch/arm64/boot/dts/freescale/s32g3.dtsi | 26 +++++++++++------------- 2 files changed, 24 insertions(+), 28 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/s32g2.dtsi b/arch/arm64/boot/dts/freescale/s32g2.dtsi index fa054bfe7d5c..e14ce5503e1f 100644 --- a/arch/arm64/boot/dts/freescale/s32g2.dtsi +++ b/arch/arm64/boot/dts/freescale/s32g2.dtsi @@ -114,20 +114,18 @@ soc@0 { #size-cells = <1>; ranges = <0 0 0 0x80000000>; - pinctrl: pinctrl@4009c240 { - compatible = "nxp,s32g2-siul2-pinctrl"; - /* MSCR0-MSCR101 registers on siul2_0 */ - reg = <0x4009c240 0x198>, - /* MSCR112-MSCR122 registers on siul2_1 */ - <0x44010400 0x2c>, - /* MSCR144-MSCR190 registers on siul2_1 */ - <0x44010480 0xbc>, - /* IMCR0-IMCR83 registers on siul2_0 */ - <0x4009ca40 0x150>, - /* IMCR119-IMCR397 registers on siul2_1 */ - <0x44010c1c 0x45c>, - /* IMCR430-IMCR495 registers on siul2_1 */ - <0x440110f8 0x108>; + siul2: siul2@4009c000 { + compatible = "nxp,s32g2-siul2"; + reg = <0x4009c000 0x179c>, + <0x44010000 0x17b0>; + reg-names = "siul20", "siul21"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&siul2 0 0 102>, <&siul2 112 112 79>; + gpio-reserved-ranges = <102 10>, <123 21>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = ; jtag_pins: jtag-pins { jtag-grp0 { diff --git a/arch/arm64/boot/dts/freescale/s32g3.dtsi b/arch/arm64/boot/dts/freescale/s32g3.dtsi index b4226a9143c8..fa43d036686f 100644 --- a/arch/arm64/boot/dts/freescale/s32g3.dtsi +++ b/arch/arm64/boot/dts/freescale/s32g3.dtsi @@ -171,20 +171,18 @@ soc@0 { #size-cells = <1>; ranges = <0 0 0 0x80000000>; - pinctrl: pinctrl@4009c240 { - compatible = "nxp,s32g2-siul2-pinctrl"; - /* MSCR0-MSCR101 registers on siul2_0 */ - reg = <0x4009c240 0x198>, - /* MSCR112-MSCR122 registers on siul2_1 */ - <0x44010400 0x2c>, - /* MSCR144-MSCR190 registers on siul2_1 */ - <0x44010480 0xbc>, - /* IMCR0-IMCR83 registers on siul2_0 */ - <0x4009ca40 0x150>, - /* IMCR119-IMCR397 registers on siul2_1 */ - <0x44010c1c 0x45c>, - /* IMCR430-IMCR495 registers on siul2_1 */ - <0x440110f8 0x108>; + siul2: siul2@4009c000 { + compatible = "nxp,s32g3-siul2"; + reg = <0x4009c000 0x179c>, + <0x44010000 0x17b0>; + reg-names = "siul20", "siul21"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&siul2 0 0 102>, <&siul2 112 112 79>; + gpio-reserved-ranges = <102 10>, <123 21>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = ; jtag_pins: jtag-pins { jtag-grp0 {