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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Maxime Coquelin , netdev@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, lftan.linux@gmail.com, leyfoon.tan@starfivetech.com Subject: [net-next v2 3/3] net: stmmac: dwmac4: Receive Watchdog Timeout is not in abnormal interrupt summary Date: Fri, 1 Nov 2024 16:23:36 +0800 Message-ID: <20241101082336.1552084-4-leyfoon.tan@starfivetech.com> X-Mailer: git-send-email 2.46.0 In-Reply-To: <20241101082336.1552084-1-leyfoon.tan@starfivetech.com> References: <20241101082336.1552084-1-leyfoon.tan@starfivetech.com> X-ClientProxiedBy: ZQ0PR01CA0015.CHNPR01.prod.partner.outlook.cn (2406:e500:c550:5::9) To ZQZPR01MB0979.CHNPR01.prod.partner.outlook.cn (2406:e500:c550:f::12) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: ZQZPR01MB0979:EE_|ZQZPR01MB1107:EE_ X-MS-Office365-Filtering-Correlation-Id: 4e61733a-76a1-4322-75b4-08dcfa4e8e5d X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|366016|52116014|7416014|41320700013|38350700014; X-Microsoft-Antispam-Message-Info: /Xh5VepZfBhi5lvrZ2i7QqXO9Gap7MtUfsl/jCoeT4xTp3RizaIJL5bln56zMBOGqppx/UEOufi3YuRXpixON9VvpjQEc00dpNCTfi8Qsxupd/7iTr+mFC+4ZXXV/RVG81gIIBzzeM+oubgzvNC1Fy8AQkxvMujQubFlTj0Z0EvBNHp4j9U4NqrMjHfz3gI2PIXaEGCO9SUpXLFMDJD1iuZhRgugr51k+PVJW4PVRuRyibPSsIqEvQ+JZfExqryYUUbOGojLj6QzZL74vgIATT78i0KPCFPWKXilfSPuAF7aeGbWveFmywbVsQ3DZePBAFjPJtVKZZtopdJXge7bpfAo5BqDuPAsV2Iaux7QBfoSh08J5F5kewH3Jfb9BsFa6OU8MqjN7uIksbbQhx4AIPN0YpS4qCJtziIsFWHq0S29Ha9qgkGk/tRDxLx4m6lZV04wKouj7sqJI371HGEmNPsd9hNjUEkFdG4U58lTYc+D6PXZk88svJK78dvD1TM9XY29aswyICpYpVHro08qpQjM9go1c099MLTRr6HhR9bPjGBBOJMrEkAhssy9nURJ/3FuI4Kz7owlZC+v2Ep7fSXnfg0u8s3Hr1OjlPkGFeWkLHST1pmED0jVNoZZcn+Q X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:ZQZPR01MB0979.CHNPR01.prod.partner.outlook.cn;PTR:;CAT:NONE;SFS:(13230040)(1800799024)(366016)(52116014)(7416014)(41320700013)(38350700014);DIR:OUT;SFP:1102; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 0lCT+H1hiyi50kWSAKXprcwYaU4Lnn79wnWppv8XURY4pA2rOsyacLrqEfu3Jr02tkk9Zc3XgFK0ORpuAXkDiYu6DTeZeHocDvzMupsnkJyoR1yY2A68708i6OJqXbOLb+hWWFi6FOs1jhh+z7Vgeiwr7tcvUBCx+u/CSe5kK5tIRFv8zypmJ/kuj7E1lAoWwfBhlFLn65iKU0Bmcgo5gr61BofRRmrUlO7p4ICPU6fyluVWo0M98UmaO7IsNZg5WgG5wnfT1OQ6P7IvxlbbQrfqun1LsA6tY1owKiBZrd55gcUXx0u0vHTRgUVmAct0II9o4P5HxmV0sbpKyj6NfWpmd0JxSqO/G8dF/BznJStNCkF9EYorRhtFrC20e41H4TaxgT4H6tEmXHOJkQGesY9BcwzB0UCh/UcsOKI6fR1XtADkkxbXLGJZ3NMJMGy8LZuSVZEZFBBPNM50B7oGvqgqAyzI1FuY9fjCvdGJqEA94JSEtEMvBHC0CkH9QRyqI4ddkpnKKYDs1PXe39ZRypccBc+ECv0sfeYbCToLQYKPHozF4t/kD2nHBWA0lBJ1Gb6b5wrOJQvJET29SIM5vd+WB1gb4w4MKe7as/4yGDMz0Qni1lfXR2owGYVdlr9TVVxuBTqsoMoE674DJWfVMi/X7LHB1N8UcmMfIj98HS0u1glLLiqNVB6M7gDq4QH0poRbJSB1Ifu5UoclWrjg5JWTd8LYVhCsF9B7/6QLlticJJjxnnf2c1pQoFjcRX1Z+yhWjfvRadRMWg/qVGKMuhabsxgavqk99TULtUBtRHSQUmoVfrehEXfonfHlHzZiV/OEtmorWSW6re0VUWNw/2XgIQF4QuM1Kuu9vNHvBKkaDA+w+J26+1Lbi736QWTSksP2fE26HxpKmPZb6YbEJtjrYUjDp6bqKo5ISdCFnqLsxWT/L8P9VLyAG8wfJC5amUvLM9ItKR1xEGX9e7nWk6fPZzsjO7R/Z7oo2QijhQXwUIpqPMGQ+MfrCyyGOKxG2dBb3i0G9yLRRdOFmlKq1DGy4OptLGPAvKB7sFpTDHDTbX1poxKF+R6974jlolcMTfdv8LExCRGGTdir+xuqIShKNddpA+FSco4PU25YYQlB+VulcO5d8xvBtZjcS4DzFo77+kfKePTs6BSxy/J5tmnY9wXUN5tXIkY6cwkRVvCs4C7GHxAX7XvE6IKMxF3IsNsoJm/FTxGTUhhvoYNdowjz9+jCruvQhFpBy7K4q57Wgylgr2Rkvo9leXuFh8uX9Efjh3zp9Wdd/1+VbkjhpwOlhKq937aCQPE2ddc+qQvISQBwPgeznto09ymeCV2JTaEQSX8EJvaMVuAkVJm90CwBlBs5eykBUkFqV6UU4zSyCDPJfmqdfECtELgASlJcw9ZEGRvhhUM78GPrV6N0QwdvuSIhCN6Pm43fDee/llwjzpvD9d0ODEAq7CUavq5VMZueGxuXiDOSXSey5q7S9PpSqVJ5A9tb6uMI5Ja3v1IzAKm2/+Afr0u60nLfYQ/I7CF15WXM3xK92Ev666HRztzXDcEFGiSy+rk3nxgJ2kiP7uiB4dzC9V4z8QqEDxHnKthNMNXLAdUw2E7+axLzP4J0Ueo8eqxsjt5vaq33Z+k= X-OriginatorOrg: starfivetech.com X-MS-Exchange-CrossTenant-Network-Message-Id: 4e61733a-76a1-4322-75b4-08dcfa4e8e5d X-MS-Exchange-CrossTenant-AuthSource: ZQZPR01MB0979.CHNPR01.prod.partner.outlook.cn X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 01 Nov 2024 08:24:08.4598 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 06fe3fa3-1221-43d3-861b-5a4ee687a85c X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: fmjVpnnHtNK709rRLo/FCYxvzproSsPXhoTBCeCYSyuCeuGOq4ZhriJJ1eCnltShdMw/Mjl9iR78ZX6I2owZpVBvQYzL7R5xc77l0EVFSp4= X-MS-Exchange-Transport-CrossTenantHeadersStamped: ZQZPR01MB1107 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241101_012418_349920_6B2D55D0 X-CRM114-Status: UNSURE ( 8.57 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The Receive Watchdog Timeout (RWT, bit[9]) is not part of Abnormal Interrupt Summary (AIS). Move the RWT handling out of the AIS condition statement. From databook, the AIS is the logical OR of the following interrupt bits: - Bit 1: Transmit Process Stopped - Bit 7: Receive Buffer Unavailable - Bit 8: Receive Process Stopped - Bit 10: Early Transmit Interrupt - Bit 12: Fatal Bus Error - Bit 13: Context Descriptor Error Signed-off-by: Ley Foon Tan --- drivers/net/ethernet/stmicro/stmmac/dwmac4_lib.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac4_lib.c b/drivers/net/ethernet/stmicro/stmmac/dwmac4_lib.c index 0d185e54eb7e..57c03d491774 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac4_lib.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac4_lib.c @@ -185,8 +185,6 @@ int dwmac4_dma_interrupt(struct stmmac_priv *priv, void __iomem *ioaddr, x->rx_buf_unav_irq++; if (unlikely(intr_status & DMA_CHAN_STATUS_RPS)) x->rx_process_stopped_irq++; - if (unlikely(intr_status & DMA_CHAN_STATUS_RWT)) - x->rx_watchdog_irq++; if (unlikely(intr_status & DMA_CHAN_STATUS_ETI)) x->tx_early_irq++; if (unlikely(intr_status & DMA_CHAN_STATUS_TPS)) { @@ -198,6 +196,10 @@ int dwmac4_dma_interrupt(struct stmmac_priv *priv, void __iomem *ioaddr, ret = tx_hard_error; } } + + if (unlikely(intr_status & DMA_CHAN_STATUS_RWT)) + x->rx_watchdog_irq++; + /* TX/RX NORMAL interrupts */ if (likely(intr_status & DMA_CHAN_STATUS_RI)) { u64_stats_update_begin(&stats->syncp);