| Message ID | 20241107-qcom_ipq_cmnpll-v6-5-a5cfe09de485@quicinc.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | Add CMN PLL clock controller driver for IPQ9574 | expand |
diff --git a/arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi b/arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi index 78f6a2e053d5..9a8692377176 100644 --- a/arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi @@ -174,8 +174,13 @@ &ref_48mhz_clk { clock-mult = <1>; }; +/* + * The frequency of xo_board_clk is fixed to 24 MHZ, which is routed + * from WiFi output clock 48 MHZ divided by 2. + */ &xo_board_clk { - clock-frequency = <24000000>; + clock-div = <2>; + clock-mult = <1>; }; &xo_clk { diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi index 8246a00a3e3e..25aed33e9358 100644 --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi @@ -32,7 +32,8 @@ sleep_clk: sleep-clk { }; xo_board_clk: xo-board-clk { - compatible = "fixed-clock"; + compatible = "fixed-factor-clock"; + clocks = <&ref_48mhz_clk>; #clock-cells = <0>; };
xo_board_clk is fixed to 24 MHZ, which is routed from WiFi output clock 48 MHZ (also being the reference clock of CMN PLL) divided 2 by analog block routing channel. Signed-off-by: Luo Jie <quic_luoj@quicinc.com> --- arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi | 7 ++++++- arch/arm64/boot/dts/qcom/ipq9574.dtsi | 3 ++- 2 files changed, 8 insertions(+), 2 deletions(-)