| Message ID | 20241113110955.3876045-3-danishanwar@ti.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | Add Clocks for ICSSG | expand |
On 13/11/2024 13:09, MD Danish Anwar wrote: > ICSSG has 7 available clocks per instance. Add all the cloks to ICSSG > nodes. ICSSG currently uses ICSSG_ICLK (clk id 20) which operates at > 250MHz. Switch ICSSG clock to ICSSG_CORE clock (clk id 0) which operates at > 333MHz. > > ICSSG_CORE clock will help get the most out of ICSSG as more cycles are > needed to fully support all ICSSG features. > > This commit also changes assigned-clock-parents of coreclk-mux to > ICSSG_CORE clock from ICSSG_ICLK. > > Performance update in dual mac mode > With ICSSG_CORE Clk @ 333MHz > Tx throughput - 934 Mbps > Rx throughput - 914 Mbps, > > With ICSSG_ICLK clk @ 250MHz, > Tx throughput - 920 Mbps > Rx throughput - 706 Mbps > > Signed-off-by: MD Danish Anwar <danishanwar@ti.com> > --- > arch/arm64/boot/dts/ti/k3-am64-main.dtsi | 22 ++++++++++++++++++++-- What about other platforms that have ICSSG? e.g. k3-am65-main.dtsi and k3-j721e-main.dtsi > 1 file changed, 20 insertions(+), 2 deletions(-) > > diff --git a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi > index c66289a4362b..324eb44c258d 100644 > --- a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi > +++ b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi > @@ -1227,6 +1227,15 @@ icssg0: icssg@30000000 { > #address-cells = <1>; > #size-cells = <1>; > ranges = <0x0 0x00 0x30000000 0x80000>; > + clocks = <&k3_clks 81 0>, /* icssg0_core_clk */ > + <&k3_clks 81 3>, /* icssg0_iep_clk */ > + <&k3_clks 81 16>, /* icssg0_rgmii_mhz_250_clk */ > + <&k3_clks 81 17>, /* icssg0_rgmii_mhz_50_clk */ > + <&k3_clks 81 18>, /* icssg0_rgmii_mhz_5_clk */ > + <&k3_clks 81 19>, /* icssg0_uart_clk */ > + <&k3_clks 81 20>; /* icssg0_iclk */ > + assigned-clocks = <&k3_clks 81 0>; > + assigned-clock-parents = <&k3_clks 81 2>; > > icssg0_mem: memories@0 { > reg = <0x0 0x2000>, > @@ -1252,7 +1261,7 @@ icssg0_coreclk_mux: coreclk-mux@3c { > clocks = <&k3_clks 81 0>, /* icssg0_core_clk */ > <&k3_clks 81 20>; /* icssg0_iclk */ > assigned-clocks = <&icssg0_coreclk_mux>; > - assigned-clock-parents = <&k3_clks 81 20>; > + assigned-clock-parents = <&k3_clks 81 0>; > }; > > icssg0_iepclk_mux: iepclk-mux@30 { > @@ -1397,6 +1406,15 @@ icssg1: icssg@30080000 { > #address-cells = <1>; > #size-cells = <1>; > ranges = <0x0 0x00 0x30080000 0x80000>; > + clocks = <&k3_clks 82 0>, /* icssg1_core_clk */ > + <&k3_clks 82 3>, /* icssg1_iep_clk */ > + <&k3_clks 82 16>, /* icssg1_rgmii_mhz_250_clk */ > + <&k3_clks 82 17>, /* icssg1_rgmii_mhz_50_clk */ > + <&k3_clks 82 18>, /* icssg1_rgmii_mhz_5_clk */ > + <&k3_clks 82 19>, /* icssg1_uart_clk */ > + <&k3_clks 82 20>; /* icssg1_iclk */ > + assigned-clocks = <&k3_clks 82 0>; > + assigned-clock-parents = <&k3_clks 82 2>; > > icssg1_mem: memories@0 { > reg = <0x0 0x2000>, > @@ -1422,7 +1440,7 @@ icssg1_coreclk_mux: coreclk-mux@3c { > clocks = <&k3_clks 82 0>, /* icssg1_core_clk */ > <&k3_clks 82 20>; /* icssg1_iclk */ > assigned-clocks = <&icssg1_coreclk_mux>; > - assigned-clock-parents = <&k3_clks 82 20>; > + assigned-clock-parents = <&k3_clks 82 0>; > }; > > icssg1_iepclk_mux: iepclk-mux@30 {
Am 13.11.24 um 12:09 schrieb MD Danish Anwar: > ICSSG has 7 available clocks per instance. Add all the cloks to ICSSG > nodes. ICSSG currently uses ICSSG_ICLK (clk id 20) which operates at > 250MHz. Switch ICSSG clock to ICSSG_CORE clock (clk id 0) which operates at > 333MHz. > > ICSSG_CORE clock will help get the most out of ICSSG as more cycles are > needed to fully support all ICSSG features. > > This commit also changes assigned-clock-parents of coreclk-mux to > ICSSG_CORE clock from ICSSG_ICLK. > > Performance update in dual mac mode > With ICSSG_CORE Clk @ 333MHz > Tx throughput - 934 Mbps > Rx throughput - 914 Mbps, > > With ICSSG_ICLK clk @ 250MHz, > Tx throughput - 920 Mbps > Rx throughput - 706 Mbps I can see similar improvements. Thank you. > > Signed-off-by: MD Danish Anwar <danishanwar@ti.com> Tested on a phyBOARD-Electra-AM64x board, Tested-by: Wadim Egorov <w.egorov@phytec.de>
On 13/11/2024 13:09, MD Danish Anwar wrote: > ICSSG has 7 available clocks per instance. Add all the cloks to ICSSG > nodes. ICSSG currently uses ICSSG_ICLK (clk id 20) which operates at > 250MHz. Switch ICSSG clock to ICSSG_CORE clock (clk id 0) which operates at > 333MHz. > > ICSSG_CORE clock will help get the most out of ICSSG as more cycles are > needed to fully support all ICSSG features. > > This commit also changes assigned-clock-parents of coreclk-mux to > ICSSG_CORE clock from ICSSG_ICLK. > > Performance update in dual mac mode > With ICSSG_CORE Clk @ 333MHz > Tx throughput - 934 Mbps > Rx throughput - 914 Mbps, > > With ICSSG_ICLK clk @ 250MHz, > Tx throughput - 920 Mbps > Rx throughput - 706 Mbps > > Signed-off-by: MD Danish Anwar <danishanwar@ti.com> It would be nice if you could send patches to update corresponding nodes in am65 and j721e platforms as well else we will start getting dtbs_check errors. Reviewed-by: Roger Quadros <rogerq@kernel.org>
diff --git a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi index c66289a4362b..324eb44c258d 100644 --- a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi @@ -1227,6 +1227,15 @@ icssg0: icssg@30000000 { #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x00 0x30000000 0x80000>; + clocks = <&k3_clks 81 0>, /* icssg0_core_clk */ + <&k3_clks 81 3>, /* icssg0_iep_clk */ + <&k3_clks 81 16>, /* icssg0_rgmii_mhz_250_clk */ + <&k3_clks 81 17>, /* icssg0_rgmii_mhz_50_clk */ + <&k3_clks 81 18>, /* icssg0_rgmii_mhz_5_clk */ + <&k3_clks 81 19>, /* icssg0_uart_clk */ + <&k3_clks 81 20>; /* icssg0_iclk */ + assigned-clocks = <&k3_clks 81 0>; + assigned-clock-parents = <&k3_clks 81 2>; icssg0_mem: memories@0 { reg = <0x0 0x2000>, @@ -1252,7 +1261,7 @@ icssg0_coreclk_mux: coreclk-mux@3c { clocks = <&k3_clks 81 0>, /* icssg0_core_clk */ <&k3_clks 81 20>; /* icssg0_iclk */ assigned-clocks = <&icssg0_coreclk_mux>; - assigned-clock-parents = <&k3_clks 81 20>; + assigned-clock-parents = <&k3_clks 81 0>; }; icssg0_iepclk_mux: iepclk-mux@30 { @@ -1397,6 +1406,15 @@ icssg1: icssg@30080000 { #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x00 0x30080000 0x80000>; + clocks = <&k3_clks 82 0>, /* icssg1_core_clk */ + <&k3_clks 82 3>, /* icssg1_iep_clk */ + <&k3_clks 82 16>, /* icssg1_rgmii_mhz_250_clk */ + <&k3_clks 82 17>, /* icssg1_rgmii_mhz_50_clk */ + <&k3_clks 82 18>, /* icssg1_rgmii_mhz_5_clk */ + <&k3_clks 82 19>, /* icssg1_uart_clk */ + <&k3_clks 82 20>; /* icssg1_iclk */ + assigned-clocks = <&k3_clks 82 0>; + assigned-clock-parents = <&k3_clks 82 2>; icssg1_mem: memories@0 { reg = <0x0 0x2000>, @@ -1422,7 +1440,7 @@ icssg1_coreclk_mux: coreclk-mux@3c { clocks = <&k3_clks 82 0>, /* icssg1_core_clk */ <&k3_clks 82 20>; /* icssg1_iclk */ assigned-clocks = <&icssg1_coreclk_mux>; - assigned-clock-parents = <&k3_clks 82 20>; + assigned-clock-parents = <&k3_clks 82 0>; }; icssg1_iepclk_mux: iepclk-mux@30 {
ICSSG has 7 available clocks per instance. Add all the cloks to ICSSG nodes. ICSSG currently uses ICSSG_ICLK (clk id 20) which operates at 250MHz. Switch ICSSG clock to ICSSG_CORE clock (clk id 0) which operates at 333MHz. ICSSG_CORE clock will help get the most out of ICSSG as more cycles are needed to fully support all ICSSG features. This commit also changes assigned-clock-parents of coreclk-mux to ICSSG_CORE clock from ICSSG_ICLK. Performance update in dual mac mode With ICSSG_CORE Clk @ 333MHz Tx throughput - 934 Mbps Rx throughput - 914 Mbps, With ICSSG_ICLK clk @ 250MHz, Tx throughput - 920 Mbps Rx throughput - 706 Mbps Signed-off-by: MD Danish Anwar <danishanwar@ti.com> --- arch/arm64/boot/dts/ti/k3-am64-main.dtsi | 22 ++++++++++++++++++++-- 1 file changed, 20 insertions(+), 2 deletions(-)