| Message ID | 20241118-sets-bxs-4-64-patch-v1-v2-2-3fd45d9fb0cf@imgtec.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | Imagination BXS-4-64 MC1 GPU support | expand |
On Mon, Nov 18, 2024 at 01:01:54PM +0000, Matt Coster wrote: > All Imagination GPUs use three clocks: core, mem and sys. All reasonably > modern Imagination GPUs also support a single-clock mode where the SoC > only hooks up core and the other two are derived internally. On GPUs which > support this mode, it is the default and most commonly used integration. > > Codify this "1 or 3" constraint in our bindings and hang the specifics off > the vendor compatible string to mirror the integration-time choice. > > Signed-off-by: Matt Coster <matt.coster@imgtec.com> > --- > Changes in v2: > - Simplified clocks constraints (P2) > - Link to v1: https://lore.kernel.org/r/20241105-sets-bxs-4-64-patch-v1-v1-2-4ed30e865892@imgtec.com > --- > .../devicetree/bindings/gpu/img,powervr-rogue.yaml | 20 +++++++++++--------- > 1 file changed, 11 insertions(+), 9 deletions(-) > > diff --git a/Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml b/Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml > index ef7070daf213277d0190fe319e202fdc597337d4..3b5a5b966585ac29ad104c7aef19881eca73ce80 100644 > --- a/Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml > +++ b/Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml > @@ -29,16 +29,16 @@ properties: > reg: > maxItems: 1 > > - clocks: > - minItems: 1 > - maxItems: 3 > + clocks: true NAK. Widest constraints always stay here. > > clock-names: > - items: > - - const: core > - - const: mem > - - const: sys > - minItems: 1 > + oneOf: > + - items: > + - const: core > + - items: > + - const: core > + - const: mem > + - const: sys Why? Sorry, this is just wrong. This deviec has specific, one clock. Anyway, this needs to use old syntax. You change here nothing. NAK > > interrupts: > maxItems: 1 > @@ -56,11 +56,13 @@ required: > additionalProperties: false > > allOf: > + # Vendor integrations using a single clock domain > - if: > properties: > compatible: > contains: > - const: ti,am62-gpu > + anyOf: Nope. That's not needed, not explained. Best regards, Krzysztof
On 11/18/24 6:31 PM, Matt Coster wrote: > All Imagination GPUs use three clocks: core, mem and sys. All reasonably > modern Imagination GPUs also support a single-clock mode where the SoC > only hooks up core and the other two are derived internally. On GPUs which > support this mode, it is the default and most commonly used integration. > > Codify this "1 or 3" constraint in our bindings and hang the specifics off > the vendor compatible string to mirror the integration-time choice. > > Signed-off-by: Matt Coster <matt.coster@imgtec.com> > --- > Changes in v2: > - Simplified clocks constraints (P2) > - Link to v1: https://lore.kernel.org/r/20241105-sets-bxs-4-64-patch-v1-v1-2-4ed30e865892@imgtec.com > --- > .../devicetree/bindings/gpu/img,powervr-rogue.yaml | 20 +++++++++++--------- > 1 file changed, 11 insertions(+), 9 deletions(-) > > diff --git a/Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml b/Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml > index ef7070daf213277d0190fe319e202fdc597337d4..3b5a5b966585ac29ad104c7aef19881eca73ce80 100644 > --- a/Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml > +++ b/Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml > @@ -29,16 +29,16 @@ properties: > reg: > maxItems: 1 > > - clocks: > - minItems: 1 > - maxItems: 3 > + clocks: true > > clock-names: > - items: > - - const: core > - - const: mem > - - const: sys > - minItems: 1 > + oneOf: > + - items: > + - const: core > + - items: > + - const: core > + - const: mem > + - const: sys Clock for GE8300 in Allwinner A133 is organized with core, bus and additional pll as input. Where "bus" controlled as gate clock and optionally using pll. If am not wrong, GE8300 also comes under rogue architecture without mem and sys clocks. Does this needs to be considered into separate bindings? Thanks, Parthiban > > interrupts: > maxItems: 1 > @@ -56,11 +56,13 @@ required: > additionalProperties: false > > allOf: > + # Vendor integrations using a single clock domain > - if: > properties: > compatible: > contains: > - const: ti,am62-gpu > + anyOf: > + - const: ti,am62-gpu > then: > properties: > clocks: >
diff --git a/Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml b/Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml index ef7070daf213277d0190fe319e202fdc597337d4..3b5a5b966585ac29ad104c7aef19881eca73ce80 100644 --- a/Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml +++ b/Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml @@ -29,16 +29,16 @@ properties: reg: maxItems: 1 - clocks: - minItems: 1 - maxItems: 3 + clocks: true clock-names: - items: - - const: core - - const: mem - - const: sys - minItems: 1 + oneOf: + - items: + - const: core + - items: + - const: core + - const: mem + - const: sys interrupts: maxItems: 1 @@ -56,11 +56,13 @@ required: additionalProperties: false allOf: + # Vendor integrations using a single clock domain - if: properties: compatible: contains: - const: ti,am62-gpu + anyOf: + - const: ti,am62-gpu then: properties: clocks:
All Imagination GPUs use three clocks: core, mem and sys. All reasonably modern Imagination GPUs also support a single-clock mode where the SoC only hooks up core and the other two are derived internally. On GPUs which support this mode, it is the default and most commonly used integration. Codify this "1 or 3" constraint in our bindings and hang the specifics off the vendor compatible string to mirror the integration-time choice. Signed-off-by: Matt Coster <matt.coster@imgtec.com> --- Changes in v2: - Simplified clocks constraints (P2) - Link to v1: https://lore.kernel.org/r/20241105-sets-bxs-4-64-patch-v1-v1-2-4ed30e865892@imgtec.com --- .../devicetree/bindings/gpu/img,powervr-rogue.yaml | 20 +++++++++++--------- 1 file changed, 11 insertions(+), 9 deletions(-)