| Message ID | 20241118-sparx5-lan969x-switch-driver-4-v3-8-3cefee5e7e3a@microchip.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | net: lan969x: add RGMII support | expand |
On Mon, Nov 18, 2024 at 02:00:54PM +0100, Daniel Machon wrote: > The lan969x switch device supports two RGMII port interfaces that can be > configured for MAC level rx and tx delays. > > Document two new properties {rx,tx}-internal-delay-ps. Make them > required properties, if the phy-mode is one of: rgmii, rgmii_id, > rgmii-rxid or rgmii-txid. Also specify accepted values. Doesn't look like they are required to me. > > Signed-off-by: Daniel Machon <daniel.machon@microchip.com> > --- > .../bindings/net/microchip,sparx5-switch.yaml | 18 ++++++++++++++++++ > 1 file changed, 18 insertions(+) > > diff --git a/Documentation/devicetree/bindings/net/microchip,sparx5-switch.yaml b/Documentation/devicetree/bindings/net/microchip,sparx5-switch.yaml > index dedfad526666..2e9ef0f7bb4b 100644 > --- a/Documentation/devicetree/bindings/net/microchip,sparx5-switch.yaml > +++ b/Documentation/devicetree/bindings/net/microchip,sparx5-switch.yaml > @@ -129,6 +129,24 @@ properties: > minimum: 0 > maximum: 383 > > + rx-internal-delay-ps: > + description: | Don't need '|' if there is not formatting to preserve. > + RGMII Receive Clock Delay defined in pico seconds, used to select > + the DLL phase shift between 1000 ps (45 degree shift at 1Gbps) and > + 3300 ps (147 degree shift at 1Gbps). A value of 0 ps will disable > + any delay. The Default is no delay. > + enum: [0, 1000, 1700, 2000, 2500, 3000, 3300] > + default: 0 > + > + tx-internal-delay-ps: > + description: | > + RGMII Transmit Clock Delay defined in pico seconds, used to select > + the DLL phase shift between 1000 ps (45 degree shift at 1Gbps) and > + 3300 ps (147 degree shift at 1Gbps). A value of 0 ps will disable > + any delay. The Default is no delay. > + enum: [0, 1000, 1700, 2000, 2500, 3000, 3300] > + default: 0 > + > required: > - reg > - phys > > -- > 2.34.1 >
Hi Rob, > > The lan969x switch device supports two RGMII port interfaces that can be > > configured for MAC level rx and tx delays. > > > > Document two new properties {rx,tx}-internal-delay-ps. Make them > > required properties, if the phy-mode is one of: rgmii, rgmii_id, > > rgmii-rxid or rgmii-txid. Also specify accepted values. > > Doesn't look like they are required to me. Commit description needs updating. Thanks for catching this! > > > > > Signed-off-by: Daniel Machon <daniel.machon@microchip.com> > > --- > > .../bindings/net/microchip,sparx5-switch.yaml | 18 ++++++++++++++++++ > > 1 file changed, 18 insertions(+) > > > > diff --git a/Documentation/devicetree/bindings/net/microchip,sparx5-switch.yaml b/Documentation/devicetree/bindings/net/microchip,sparx5-switch.yaml > > index dedfad526666..2e9ef0f7bb4b 100644 > > --- a/Documentation/devicetree/bindings/net/microchip,sparx5-switch.yaml > > +++ b/Documentation/devicetree/bindings/net/microchip,sparx5-switch.yaml > > @@ -129,6 +129,24 @@ properties: > > minimum: 0 > > maximum: 383 > > > > + rx-internal-delay-ps: > > + description: | > > Don't need '|' if there is not formatting to preserve. Ack. > > > + RGMII Receive Clock Delay defined in pico seconds, used to select > > + the DLL phase shift between 1000 ps (45 degree shift at 1Gbps) and > > + 3300 ps (147 degree shift at 1Gbps). A value of 0 ps will disable > > + any delay. The Default is no delay. > > + enum: [0, 1000, 1700, 2000, 2500, 3000, 3300] > > + default: 0 > > + > > + tx-internal-delay-ps: > > + description: | > > + RGMII Transmit Clock Delay defined in pico seconds, used to select > > + the DLL phase shift between 1000 ps (45 degree shift at 1Gbps) and > > + 3300 ps (147 degree shift at 1Gbps). A value of 0 ps will disable > > + any delay. The Default is no delay. > > + enum: [0, 1000, 1700, 2000, 2500, 3000, 3300] > > + default: 0 > > + > > required: > > - reg > > - phys > > > > -- > > 2.34.1 > > /Daniel
diff --git a/Documentation/devicetree/bindings/net/microchip,sparx5-switch.yaml b/Documentation/devicetree/bindings/net/microchip,sparx5-switch.yaml index dedfad526666..2e9ef0f7bb4b 100644 --- a/Documentation/devicetree/bindings/net/microchip,sparx5-switch.yaml +++ b/Documentation/devicetree/bindings/net/microchip,sparx5-switch.yaml @@ -129,6 +129,24 @@ properties: minimum: 0 maximum: 383 + rx-internal-delay-ps: + description: | + RGMII Receive Clock Delay defined in pico seconds, used to select + the DLL phase shift between 1000 ps (45 degree shift at 1Gbps) and + 3300 ps (147 degree shift at 1Gbps). A value of 0 ps will disable + any delay. The Default is no delay. + enum: [0, 1000, 1700, 2000, 2500, 3000, 3300] + default: 0 + + tx-internal-delay-ps: + description: | + RGMII Transmit Clock Delay defined in pico seconds, used to select + the DLL phase shift between 1000 ps (45 degree shift at 1Gbps) and + 3300 ps (147 degree shift at 1Gbps). A value of 0 ps will disable + any delay. The Default is no delay. + enum: [0, 1000, 1700, 2000, 2500, 3000, 3300] + default: 0 + required: - reg - phys
The lan969x switch device supports two RGMII port interfaces that can be configured for MAC level rx and tx delays. Document two new properties {rx,tx}-internal-delay-ps. Make them required properties, if the phy-mode is one of: rgmii, rgmii_id, rgmii-rxid or rgmii-txid. Also specify accepted values. Signed-off-by: Daniel Machon <daniel.machon@microchip.com> --- .../bindings/net/microchip,sparx5-switch.yaml | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+)