@@ -128,6 +128,32 @@ struct clk_hw *imx_get_clk_hw_by_name(struct device_node *np, const char *name)
}
EXPORT_SYMBOL_GPL(imx_get_clk_hw_by_name);
+#if defined(CONFIG_CLK_IMX8MM) || defined(CONFIG_CLK_IMX8MN) || \
+ defined(CONFIG_CLK_IMX8MP) || defined(CONFIG_CLK_IMX8MQ)
+struct clk_hw *imx8m_anatop_get_clk_hw(int id)
+{
+#if defined(CONFIG_CLK_IMX8MQ)
+ const char *compatible = "fsl,imx8mq-anatop";
+#else
+ const char *compatible = "fsl,imx8mm-anatop";
+#endif
+ struct device_node *np;
+ struct of_phandle_args args;
+ struct clk_hw *hw;
+
+ np = of_find_compatible_node(NULL, NULL, compatible);
+ args.np = np;
+ args.args_count = 1;
+ args.args[0] = id;
+ of_node_put(np);
+
+ hw = __clk_get_hw(of_clk_get_from_provider(&args));
+ pr_debug("%s: got clk: %s\n", __func__, clk_hw_get_name(hw));
+ return hw;
+}
+EXPORT_SYMBOL_GPL(imx8m_anatop_get_clk_hw);
+#endif
+
/*
* This fixups the register CCM_CSCMR1 write value.
* The write/read/divider values of the aclk_podf field
@@ -487,4 +487,10 @@ struct clk_hw *imx_clk_gpr_mux(const char *name, const char *compatible,
u32 reg, const char **parent_names,
u8 num_parents, const u32 *mux_table, u32 mask);
+
+#if defined(CONFIG_CLK_IMX8MM) || defined(CONFIG_CLK_IMX8MN) || \
+ defined(CONFIG_CLK_IMX8MP) || defined(CONFIG_CLK_IMX8MQ)
+struct clk_hw *imx8m_anatop_get_clk_hw(int id);
+#endif
+
#endif
Get the hw of a clock registered by the anatop module. This function is preparatory for future developments. Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com> - Added in v4 --- (no changes since v1) drivers/clk/imx/clk.c | 26 ++++++++++++++++++++++++++ drivers/clk/imx/clk.h | 6 ++++++ 2 files changed, 32 insertions(+)