| Message ID | 20241203-gs101-phy-lanes-orientation-dts-v2-2-1412783a6b01@linaro.org (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | Google Pixel 6 (oriole): TCPCI enablement & USB updates | expand |
On Tue, 3 Dec 2024 at 12:40, André Draszik <andre.draszik@linaro.org> wrote: > > Turns out there are some additional registers in the phy region, update > the DT accordingly. > > Signed-off-by: André Draszik <andre.draszik@linaro.org> > --- Reviewed-by: Peter Griffin <peter.griffin@linaro.org> Tested-by: Peter Griffin <peter.griffin@linaro.org>
diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot/dts/exynos/google/gs101.dtsi index 302c5beb224a..18d4e7852a1a 100644 --- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi +++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi @@ -1267,7 +1267,7 @@ cmu_hsi0: clock-controller@11000000 { usbdrd31_phy: phy@11100000 { compatible = "google,gs101-usb31drd-phy"; - reg = <0x11100000 0x0100>, + reg = <0x11100000 0x0200>, <0x110f0000 0x0800>, <0x110e0000 0x2800>; reg-names = "phy", "pcs", "pma";
Turns out there are some additional registers in the phy region, update the DT accordingly. Signed-off-by: André Draszik <andre.draszik@linaro.org> --- arch/arm64/boot/dts/exynos/google/gs101.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)