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Wed, 04 Dec 2024 03:05:37 -0800 (PST) Received: from [192.168.1.51] ([83.45.91.239]) by smtp.gmail.com with ESMTPSA id d75a77b69052e-466c407e11esm72245921cf.42.2024.12.04.03.05.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Dec 2024 03:05:37 -0800 (PST) From: Enric Balletbo i Serra Date: Wed, 04 Dec 2024 12:05:26 +0100 Subject: [PATCH v2] arm64: dts: ti: k3-am69-sk: Add USB SuperSpeed support MIME-Version: 1.0 Message-Id: <20241204-am69sk-dt-usb-v2-1-d59b2ac45c6e@redhat.com> X-B4-Tracking: v=1; b=H4sIAHU3UGcC/3XMQQ7CIBCF4as0s3ZMIVLBlfcwXdAyCDEtBpBoG u4udu/yf8n7NkgUPSW4dBtEKj75sLbghw5mp9c7oTetgff8xBgfUC+DSg80GV9pQqmY7MkKaaW B9nlGsv69e7extfMph/jZ+cJ+6z+pMGSotRCazHmSiq6RjNP5OIcFxlrrF8JCOICrAAAA X-Change-ID: 20241126-am69sk-dt-usb-89180ef58f8d To: Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Dasnavis Sabiya , Enric Balletbo i Serra X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1733310335; l=2663; i=eballetb@redhat.com; s=20241113; h=from:subject:message-id; bh=FMm9H6sLzpHevS+BDD1ZhChgz+IY/7iaPRnVhXYcLc8=; b=4mJOPQHNLdI0jquYC0yWN66Urs5UsMcZCIcQ7ufmqldmUjbtjc5nmPxy0Lo9kBftq27tGXGyv 6Wq10Ov1mjzBotzxZIFBNGQOFnYtMXLNGUm2mAm7c483cKISscpv0Mw X-Developer-Key: i=eballetb@redhat.com; a=ed25519; pk=xAM6APjLnjm98JkE7JdP1GytrxFUrcDLr+fvzW1Dlyw= X-Mimecast-Spam-Score: 0 X-Mimecast-MFC-PROC-ID: ivqB1LRc-av-_pCF37DLEbz6JTf8iePcukwlYUKLL5w_1733310338 X-Mimecast-Originator: redhat.com X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241204_030541_141011_9D8F57E1 X-CRM114-Status: GOOD ( 16.66 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Dasnavis Sabiya AM69 SK board has two stacked USB3 connectors: 1. USB3 (Stacked TypeA + TypeC) 2. USB3 TypeA Hub interfaced through TUSB8041. The board uses SERDES0 Lane 3 for USB3 IP. So update the SerDes lane info for PCIe and USB. Add the pin mux data and enable USB 3.0 support with its respective SERDES settings. Signed-off-by: Dasnavis Sabiya Signed-off-by: Enric Balletbo i Serra --- I've been carrying this patch for quite long time in my builds to have support for USB on my AM69-SK board without problems. For some reason this patch was never send to upstream or I couldn't find it. So I took the opportunity, now that I rebased my build, to send upstream. I have maintained the original author of the downstream patch as is basically his work. --- Changes in v2: - Set dr_mode to otg to fully describe the hardware proprieties - Link to v1: https://lore.kernel.org/r/20241126-am69sk-dt-usb-v1-1-aa55aed7b89e@redhat.com --- arch/arm64/boot/dts/ti/k3-am69-sk.dts | 33 +++++++++++++++++++++++++++++++++ 1 file changed, 33 insertions(+) --- base-commit: 7eef7e306d3c40a0c5b9ff6adc9b273cc894dbd5 change-id: 20241126-am69sk-dt-usb-89180ef58f8d Best regards, diff --git a/arch/arm64/boot/dts/ti/k3-am69-sk.dts b/arch/arm64/boot/dts/ti/k3-am69-sk.dts index 1e36965a14032ca07143230855e04b9549f1d0d1..353579dedb19a4f9809913570143666f4c4ec53e 100644 --- a/arch/arm64/boot/dts/ti/k3-am69-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am69-sk.dts @@ -484,6 +484,12 @@ J784S4_IOPAD(0x09C, PIN_OUTPUT, 0) /* (AF35) MCAN7_TX */ >; }; + main_usbss0_pins_default: main-usbss0-default-pins { + pinctrl-single,pins = < + J784S4_IOPAD(0x0EC, PIN_OUTPUT, 6) /* (AN37) TIMER_IO1.USB0_DRVVBUS */ + >; + }; + }; &wkup_pmx0 { @@ -1299,6 +1305,14 @@ serdes0_pcie_link: phy@0 { cdns,phy-type = ; resets = <&serdes_wiz0 1>, <&serdes_wiz0 2>, <&serdes_wiz0 3>; }; + + serdes0_usb_link: phy@3 { + reg = <3>; + cdns,num-lanes = <1>; + #phy-cells = <0>; + cdns,phy-type = ; + resets = <&serdes_wiz0 4>; + }; }; &serdes_wiz1 { @@ -1339,3 +1353,22 @@ &pcie3_rc { phy-names = "pcie-phy"; num-lanes = <1>; }; + +&usb_serdes_mux { + idle-states = <0>; /* USB0 to SERDES0 */ +}; + +&usbss0 { + status = "okay"; + pinctrl-0 = <&main_usbss0_pins_default>; + pinctrl-names = "default"; + ti,vbus-divider; +}; + +&usb0 { + status = "okay"; + dr_mode = "otg"; + maximum-speed = "super-speed"; + phys = <&serdes0_usb_link>; + phy-names = "cdns3,usb3-phy"; +};