new file mode 100644
@@ -0,0 +1,105 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/net/dsa/airoha,an8855-switch.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Airoha AN8855 Gigabit Switch
+
+maintainers:
+ - Christian Marangi <ansuelsmth@gmail.com>
+
+description: >
+ Airoha AN8855 is a 5-port Gigabit Switch.
+
+ It does expose the 5 Internal PHYs on the MDIO bus and each port
+ can access the Switch register space by configurting the PHY page.
+
+ Each internal PHY might require calibration with the fused EFUSE on
+ the switch exposed by the Airoha AN8855 SoC NVMEM.
+
+$ref: dsa.yaml#
+
+properties:
+ compatible:
+ const: airoha,an8855-switch
+
+ reset-gpios:
+ description:
+ GPIO to be used to reset the whole device
+ maxItems: 1
+
+ airoha,ext-surge:
+ $ref: /schemas/types.yaml#/definitions/flag
+ description:
+ Calibrate the internal PHY with the calibration values stored in EFUSE
+ for the r50Ohm values.
+
+required:
+ - compatible
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+
+ ethernet-switch {
+ compatible = "airoha,an8855-switch";
+ reset-gpios = <&pio 39 0>;
+
+ airoha,ext-surge;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ label = "lan1";
+ phy-mode = "internal";
+ phy-handle = <&internal_phy1>;
+ };
+
+ port@1 {
+ reg = <1>;
+ label = "lan2";
+ phy-mode = "internal";
+ phy-handle = <&internal_phy2>;
+ };
+
+ port@2 {
+ reg = <2>;
+ label = "lan3";
+ phy-mode = "internal";
+ phy-handle = <&internal_phy3>;
+ };
+
+ port@3 {
+ reg = <3>;
+ label = "lan4";
+ phy-mode = "internal";
+ phy-handle = <&internal_phy4>;
+ };
+
+ port@4 {
+ reg = <4>;
+ label = "wan";
+ phy-mode = "internal";
+ phy-handle = <&internal_phy5>;
+ };
+
+ port@5 {
+ reg = <5>;
+ label = "cpu";
+ ethernet = <&gmac0>;
+ phy-mode = "2500base-x";
+
+ fixed-link {
+ speed = <2500>;
+ full-duplex;
+ pause;
+ };
+ };
+ };
+ };
@@ -718,6 +718,7 @@ L: linux-mediatek@lists.infradead.org (moderated for non-subscribers)
L: netdev@vger.kernel.org
S: Maintained
F: Documentation/devicetree/bindings/net/airoha,an8855-mdio.yaml
+F: Documentation/devicetree/bindings/net/dsa/airoha,an8855-switch.yaml
F: Documentation/devicetree/bindings/nvmem/airoha,an8855-efuse.yaml
AIROHA ETHERNET DRIVER
Document support for Airoha AN8855 5-port Gigabit Switch. It does expose the 5 Internal PHYs on the MDIO bus and each port can access the Switch register space by configurting the PHY page. Each internal PHY might require calibration with the fused EFUSE on the switch exposed by the Airoha AN8855 SoC NVMEM. Signed-off-by: Christian Marangi <ansuelsmth@gmail.com> --- .../net/dsa/airoha,an8855-switch.yaml | 105 ++++++++++++++++++ MAINTAINERS | 1 + 2 files changed, 106 insertions(+) create mode 100644 Documentation/devicetree/bindings/net/dsa/airoha,an8855-switch.yaml