diff mbox series

[v3,2/3] dt-bindings: pinctrl: add header for PCA9555 GPIO extender bindings on some Rockchip-based devices

Message ID 20241215032507.4739-3-shimrrashai@gmail.com (mailing list archive)
State New
Headers show
Series arm64: dts: rockchip: Add Firefly ITX-3588J Board | expand

Commit Message

Shimrra Shai Dec. 15, 2024, 3:24 a.m. UTC
It seemed a bit disputed whether this was actually necessary, but I am
including it nonetheless. It makes it slightly clearer how the pins on the
PCA9555 GPIO extender used on the board are actuated than would be evident
from the numbers alone, since according to the spec sheets for it by NXP:

https://www.nxp.com/docs/en/data-sheet/PCA9555.pdf

there are two banks of controllable pins, IO0 and IO1, which are labeled
equivalently to the labels provided below.

Also sorry @Heiko Stübner for adding your name on it; I had cut this off a
BSP source file that was longer. Since this file contains only this
isolated section, which was written by someone else, I put their authorship
on it instead. Unfortunately I do not know who "daijh" is, only that they
used that handle on GitLab to submit this code piece and I got the
indicated email address.

Signed-off-by: Shimrra Shai <shimrrashai@gmail.com>
---
 .../dt-bindings/pinctrl/rockchip-pca9555.h    | 31 +++++++++++++++++++
 1 file changed, 31 insertions(+)
 create mode 100644 include/dt-bindings/pinctrl/rockchip-pca9555.h

Comments

Krzysztof Kozlowski Dec. 16, 2024, 9:26 a.m. UTC | #1
On Sat, Dec 14, 2024 at 09:24:54PM -0600, Shimrra Shai wrote:
> It seemed a bit disputed whether this was actually necessary, but I am
> including it nonetheless. It makes it slightly clearer how the pins on the
> PCA9555 GPIO extender used on the board are actuated than would be evident
> from the numbers alone, since according to the spec sheets for it by NXP:
> 
> https://www.nxp.com/docs/en/data-sheet/PCA9555.pdf
> 
> there are two banks of controllable pins, IO0 and IO1, which are labeled
> equivalently to the labels provided below.
> 
> Also sorry @Heiko Stübner for adding your name on it; I had cut this off a
> BSP source file that was longer. Since this file contains only this
> isolated section, which was written by someone else, I put their authorship
> on it instead. Unfortunately I do not know who "daijh" is, only that they
> used that handle on GitLab to submit this code piece and I got the
> indicated email address.
> 
> Signed-off-by: Shimrra Shai <shimrrashai@gmail.com>
> ---
>  .../dt-bindings/pinctrl/rockchip-pca9555.h    | 31 +++++++++++++++++++
>  1 file changed, 31 insertions(+)
>  create mode 100644 include/dt-bindings/pinctrl/rockchip-pca9555.h
> 
> diff --git a/include/dt-bindings/pinctrl/rockchip-pca9555.h b/include/dt-bindings/pinctrl/rockchip-pca9555.h
> new file mode 100644
> index 000000000..21ca99488
> --- /dev/null
> +++ b/include/dt-bindings/pinctrl/rockchip-pca9555.h
> @@ -0,0 +1,31 @@
> +/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
> +/*
> + * Bindings for the PCA9555 GPIO extender used on some Rockchip devices, e.g.
> + * Firefly.
> + *
> + * Copyright (C) 2022 Zhongshan Tianqi Intelligent Technology Co., Ltd.
> + * Authors: daijh <djh@t-chip.com.cn>
> + *          Shimrra Shai <shimrrashai@gmail.com>
> + */
> +
> +#ifndef __ROCKCHIP_PCA9555_H__
> +#define __ROCKCHIP_PCA9555_H__
> +
> +#define PCA_IO0_0          0

1. There is no user of these bindings.
2. It's meaningless to map 0 to 0...

Drop entire patch.

Best regards,
Krzysztof
diff mbox series

Patch

diff --git a/include/dt-bindings/pinctrl/rockchip-pca9555.h b/include/dt-bindings/pinctrl/rockchip-pca9555.h
new file mode 100644
index 000000000..21ca99488
--- /dev/null
+++ b/include/dt-bindings/pinctrl/rockchip-pca9555.h
@@ -0,0 +1,31 @@ 
+/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
+/*
+ * Bindings for the PCA9555 GPIO extender used on some Rockchip devices, e.g.
+ * Firefly.
+ *
+ * Copyright (C) 2022 Zhongshan Tianqi Intelligent Technology Co., Ltd.
+ * Authors: daijh <djh@t-chip.com.cn>
+ *          Shimrra Shai <shimrrashai@gmail.com>
+ */
+
+#ifndef __ROCKCHIP_PCA9555_H__
+#define __ROCKCHIP_PCA9555_H__
+
+#define PCA_IO0_0          0
+#define PCA_IO0_1          1
+#define PCA_IO0_2          2
+#define PCA_IO0_3          3
+#define PCA_IO0_4          4
+#define PCA_IO0_5          5
+#define PCA_IO0_6          6
+#define PCA_IO0_7          7
+#define PCA_IO1_0          8
+#define PCA_IO1_1          9
+#define PCA_IO1_2          10
+#define PCA_IO1_3          11
+#define PCA_IO1_4          12
+#define PCA_IO1_5          13
+#define PCA_IO1_6          14
+#define PCA_IO1_7          15
+
+#endif