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[65.128.205.244]) by smtp.gmail.com with ESMTPSA id e9e14a558f8ab-3b2482298c6sm7755575ab.31.2024.12.14.19.27.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 14 Dec 2024 19:27:18 -0800 (PST) From: Shimrra Shai To: linux-kernel@vger.kernel.org Cc: conor+dt@kernel.org, devicetree@vger.kernel.org, heiko@sntech.de, krzk+dt@kernel.org, linux-arm-kernel@lists.infradead.org, linux-pm@vger.kernel.org, linux-rockchip@lists.infradead.org, robh@kernel.org, Shimrra Shai Subject: [PATCH v3 2/3] dt-bindings: pinctrl: add header for PCA9555 GPIO extender bindings on some Rockchip-based devices Date: Sat, 14 Dec 2024 21:24:54 -0600 Message-ID: <20241215032507.4739-3-shimrrashai@gmail.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241215032507.4739-1-shimrrashai@gmail.com> References: <20241215032507.4739-1-shimrrashai@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241214_192720_746371_F5A61D18 X-CRM114-Status: GOOD ( 15.00 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org It seemed a bit disputed whether this was actually necessary, but I am including it nonetheless. It makes it slightly clearer how the pins on the PCA9555 GPIO extender used on the board are actuated than would be evident from the numbers alone, since according to the spec sheets for it by NXP: https://www.nxp.com/docs/en/data-sheet/PCA9555.pdf there are two banks of controllable pins, IO0 and IO1, which are labeled equivalently to the labels provided below. Also sorry @Heiko Stübner for adding your name on it; I had cut this off a BSP source file that was longer. Since this file contains only this isolated section, which was written by someone else, I put their authorship on it instead. Unfortunately I do not know who "daijh" is, only that they used that handle on GitLab to submit this code piece and I got the indicated email address. Signed-off-by: Shimrra Shai --- .../dt-bindings/pinctrl/rockchip-pca9555.h | 31 +++++++++++++++++++ 1 file changed, 31 insertions(+) create mode 100644 include/dt-bindings/pinctrl/rockchip-pca9555.h diff --git a/include/dt-bindings/pinctrl/rockchip-pca9555.h b/include/dt-bindings/pinctrl/rockchip-pca9555.h new file mode 100644 index 000000000..21ca99488 --- /dev/null +++ b/include/dt-bindings/pinctrl/rockchip-pca9555.h @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR MIT */ +/* + * Bindings for the PCA9555 GPIO extender used on some Rockchip devices, e.g. + * Firefly. + * + * Copyright (C) 2022 Zhongshan Tianqi Intelligent Technology Co., Ltd. + * Authors: daijh + * Shimrra Shai + */ + +#ifndef __ROCKCHIP_PCA9555_H__ +#define __ROCKCHIP_PCA9555_H__ + +#define PCA_IO0_0 0 +#define PCA_IO0_1 1 +#define PCA_IO0_2 2 +#define PCA_IO0_3 3 +#define PCA_IO0_4 4 +#define PCA_IO0_5 5 +#define PCA_IO0_6 6 +#define PCA_IO0_7 7 +#define PCA_IO1_0 8 +#define PCA_IO1_1 9 +#define PCA_IO1_2 10 +#define PCA_IO1_3 11 +#define PCA_IO1_4 12 +#define PCA_IO1_5 13 +#define PCA_IO1_6 14 +#define PCA_IO1_7 15 + +#endif