| Message ID | 20241217201708.3320673-1-derek.foreman@collabora.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | drm/rockchip: Don't change hdmi reference clock rate | expand |
On 12/17/24 10:17 PM, Derek Foreman wrote: > The code that changes hdmi->ref_clk was accidentally copied from > downstream code that sets a different clock. We don't actually > want to set any clock here at all. > > Setting this clock incorrectly leads to incorrect timings for > DDC, CEC, and HDCP signal generation. > > No Fixes listed, as the theoretical timing error in DDC appears to > still be within tolerances and harmless - and HDCP and CEC are not > yet supported. > > Signed-off-by: Derek Foreman <derek.foreman@collabora.com> > --- > drivers/gpu/drm/rockchip/dw_hdmi_qp-rockchip.c | 13 ------------- > 1 file changed, 13 deletions(-) Reviewed-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
diff --git a/drivers/gpu/drm/rockchip/dw_hdmi_qp-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi_qp-rockchip.c index e498767a0a66..cebd72bf1ef2 100644 --- a/drivers/gpu/drm/rockchip/dw_hdmi_qp-rockchip.c +++ b/drivers/gpu/drm/rockchip/dw_hdmi_qp-rockchip.c @@ -54,7 +54,6 @@ struct rockchip_hdmi_qp { struct regmap *regmap; struct regmap *vo_regmap; struct rockchip_encoder encoder; - struct clk *ref_clk; struct dw_hdmi_qp *hdmi; struct phy *phy; struct gpio_desc *enable_gpio; @@ -81,7 +80,6 @@ static void dw_hdmi_qp_rockchip_encoder_enable(struct drm_encoder *encoder) if (crtc && crtc->state) { rate = drm_hdmi_compute_mode_clock(&crtc->state->adjusted_mode, 8, HDMI_COLORSPACE_RGB); - clk_set_rate(hdmi->ref_clk, rate); /* * FIXME: Temporary workaround to pass pixel clock rate * to the PHY driver until phy_configure_opts_hdmi @@ -330,17 +328,6 @@ static int dw_hdmi_qp_rockchip_bind(struct device *dev, struct device *master, return ret; } - for (i = 0; i < ret; i++) { - if (!strcmp(clks[i].id, "ref")) { - hdmi->ref_clk = clks[1].clk; - break; - } - } - if (!hdmi->ref_clk) { - drm_err(hdmi, "Missing ref clock\n"); - return -EINVAL; - } - hdmi->enable_gpio = devm_gpiod_get_optional(hdmi->dev, "enable", GPIOD_OUT_HIGH); if (IS_ERR(hdmi->enable_gpio)) {
The code that changes hdmi->ref_clk was accidentally copied from downstream code that sets a different clock. We don't actually want to set any clock here at all. Setting this clock incorrectly leads to incorrect timings for DDC, CEC, and HDCP signal generation. No Fixes listed, as the theoretical timing error in DDC appears to still be within tolerances and harmless - and HDCP and CEC are not yet supported. Signed-off-by: Derek Foreman <derek.foreman@collabora.com> --- drivers/gpu/drm/rockchip/dw_hdmi_qp-rockchip.c | 13 ------------- 1 file changed, 13 deletions(-)