@@ -26,9 +26,11 @@ / {
aliases {
dp-intf0 = &dp_intf0;
dp-intf1 = &dp_intf1;
+ dsc0 = &dsc0;
ethdr0 = ðdr0;
gce0 = &gce0;
gce1 = &gce1;
+ merge0 = &merge0;
merge1 = &merge1;
merge2 = &merge2;
merge3 = &merge3;
@@ -2880,6 +2882,15 @@ disp_dsi0: dsi@1c008000 {
status = "disabled";
};
+ dsc0: dsc@1c009000 {
+ compatible = "mediatek,mt8188-disp-dsc", "mediatek,mt8195-disp-dsc";
+ reg = <0 0x1c009000 0 0x1000>;
+ clocks = <&vdosys0 CLK_VDO0_DSC_WRAP0>;
+ interrupts = <GIC_SPI 645 IRQ_TYPE_LEVEL_HIGH 0>;
+ power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>;
+ mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x9000 0x1000>;
+ };
+
disp_dsi1: dsi@1c012000 {
compatible = "mediatek,mt8188-dsi";
reg = <0 0x1c012000 0 0x1000>;
@@ -2895,6 +2906,17 @@ disp_dsi1: dsi@1c012000 {
status = "disabled";
};
+ merge0: merge0@1c014000 {
+ compatible = "mediatek,mt8188-disp-merge", "mediatek,mt8195-disp-merge";
+ reg = <0 0x1c014000 0 0x1000>;
+ clocks = <&vdosys0 CLK_VDO0_VPP_MERGE0>,
+ <&vdosys1 CLK_VDO1_MERGE_VDO1_DL_ASYNC>;
+ clock-names = "merge", "merge_async";
+ interrupts = <GIC_SPI 656 IRQ_TYPE_LEVEL_HIGH 0>;
+ power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>;
+ mediatek,gce-client-reg = <&gce0 SUBSYS_1c01XXXX 0x4000 0x1000>;
+ };
+
dp_intf0: dp-intf@1c015000 {
compatible = "mediatek,mt8188-dp-intf";
reg = <0 0x1c015000 0 0x1000>;
Add nodes for the DSC0 and MERGE0 blocks, located in VDOSYS0 and necessary to add support for Display Stream Compression with a display pipeline that looks like: [other components] -> DSC0 -> MERGE0 -> Display Interface Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> --- arch/arm64/boot/dts/mediatek/mt8188.dtsi | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+)