| Message ID | 20250120130119.671119-8-svarbanov@suse.de (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Add PCIe support for bcm2712 | expand |
On Mon, Jan 20, 2025 at 8:01 AM Stanimir Varbanov <svarbanov@suse.de> wrote: > > The default input reference clock for the PHY PLL is 100Mhz, except for > some devices where it is 54Mhz like bcm2712C1 and bcm2712D0. > > To implement this adjustments introduce a new .post_setup op in > pcie_cfg_data and call it at the end of brcm_pcie_setup function. > > The bcm2712 .post_setup callback implements the required MDIO writes that > switch the PLL refclk and also change PHY PM clock period. > > Without this RPi5 PCIex1 is unable to enumerate endpoint devices on > the expansion connector. > > Signed-off-by: Stanimir Varbanov <svarbanov@suse.de> > Reviewed-by: Florian Fainelli <florian.fainelli@broadcom.com> > --- > v4 -> v5: > - Updated a comment (Jim). > > drivers/pci/controller/pcie-brcmstb.c | 44 +++++++++++++++++++++++++++ > 1 file changed, 44 insertions(+) > > diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/controller/pcie-brcmstb.c > index 50607df34a66..03396a9d97be 100644 > --- a/drivers/pci/controller/pcie-brcmstb.c > +++ b/drivers/pci/controller/pcie-brcmstb.c > @@ -55,6 +55,10 @@ > #define PCIE_RC_DL_MDIO_WR_DATA 0x1104 > #define PCIE_RC_DL_MDIO_RD_DATA 0x1108 > > +#define PCIE_RC_PL_PHY_CTL_15 0x184c > +#define PCIE_RC_PL_PHY_CTL_15_DIS_PLL_PD_MASK 0x400000 > +#define PCIE_RC_PL_PHY_CTL_15_PM_CLK_PERIOD_MASK 0xff > + > #define PCIE_MISC_MISC_CTRL 0x4008 > #define PCIE_MISC_MISC_CTRL_PCIE_RCB_64B_MODE_MASK 0x80 > #define PCIE_MISC_MISC_CTRL_PCIE_RCB_MPS_MODE_MASK 0x400 > @@ -251,6 +255,7 @@ struct pcie_cfg_data { > u8 num_inbound_wins; > int (*perst_set)(struct brcm_pcie *pcie, u32 val); > int (*bridge_sw_init_set)(struct brcm_pcie *pcie, u32 val); > + int (*post_setup)(struct brcm_pcie *pcie); > }; > > struct subdev_regulators { > @@ -826,6 +831,38 @@ static int brcm_pcie_perst_set_generic(struct brcm_pcie *pcie, u32 val) > return 0; > } > > +static int brcm_pcie_post_setup_bcm2712(struct brcm_pcie *pcie) > +{ > + const u16 data[] = { 0x50b9, 0xbda1, 0x0094, 0x97b4, 0x5030, 0x5030, 0x0007 }; > + const u8 regs[] = { 0x16, 0x17, 0x18, 0x19, 0x1b, 0x1c, 0x1e }; > + int ret, i; > + u32 tmp; > + > + /* Allow a 54MHz (xosc) refclk source */ > + ret = brcm_pcie_mdio_write(pcie->base, MDIO_PORT0, SET_ADDR_OFFSET, 0x1600); > + if (ret < 0) > + return ret; > + > + for (i = 0; i < ARRAY_SIZE(regs); i++) { > + ret = brcm_pcie_mdio_write(pcie->base, MDIO_PORT0, regs[i], data[i]); > + if (ret < 0) > + return ret; > + } > + > + usleep_range(100, 200); > + > + /* > + * Set L1SS sub-state timers to avoid lengthy state transitions, > + * PM clock period is 18.52ns (1/54MHz, round down). > + */ > + tmp = readl(pcie->base + PCIE_RC_PL_PHY_CTL_15); > + tmp &= ~PCIE_RC_PL_PHY_CTL_15_PM_CLK_PERIOD_MASK; > + tmp |= 0x12; > + writel(tmp, pcie->base + PCIE_RC_PL_PHY_CTL_15); > + > + return 0; > +} > + > static void add_inbound_win(struct inbound_win *b, u8 *count, u64 size, > u64 cpu_addr, u64 pci_offset) > { > @@ -1189,6 +1226,12 @@ static int brcm_pcie_setup(struct brcm_pcie *pcie) > PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR2_MASK); > writel(tmp, base + PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1); > > + if (pcie->cfg->post_setup) { > + ret = pcie->cfg->post_setup(pcie); > + if (ret < 0) > + return ret; > + } > + > return 0; > } > > @@ -1715,6 +1758,7 @@ static const struct pcie_cfg_data bcm2712_cfg = { > .soc_base = BCM7712, > .perst_set = brcm_pcie_perst_set_7278, > .bridge_sw_init_set = brcm_pcie_bridge_sw_init_set_generic, > + .post_setup = brcm_pcie_post_setup_bcm2712, > .quirks = CFG_QUIRK_AVOID_BRIDGE_SHUTDOWN, > .num_inbound_wins = 10, > }; > -- > 2.47.0 > Hi Stan, Any reason you didn't make this a quirk like the other commit? Reviewed-by: Jim Quinlan <james.quinlan@broadcom.com>
Hi Jim, On 1/31/25 6:08 PM, Jim Quinlan wrote: > On Mon, Jan 20, 2025 at 8:01 AM Stanimir Varbanov <svarbanov@suse.de> wrote: >> >> The default input reference clock for the PHY PLL is 100Mhz, except for >> some devices where it is 54Mhz like bcm2712C1 and bcm2712D0. >> >> To implement this adjustments introduce a new .post_setup op in >> pcie_cfg_data and call it at the end of brcm_pcie_setup function. >> >> The bcm2712 .post_setup callback implements the required MDIO writes that >> switch the PLL refclk and also change PHY PM clock period. >> >> Without this RPi5 PCIex1 is unable to enumerate endpoint devices on >> the expansion connector. >> >> Signed-off-by: Stanimir Varbanov <svarbanov@suse.de> >> Reviewed-by: Florian Fainelli <florian.fainelli@broadcom.com> >> --- >> v4 -> v5: >> - Updated a comment (Jim). >> >> drivers/pci/controller/pcie-brcmstb.c | 44 +++++++++++++++++++++++++++ >> 1 file changed, 44 insertions(+) >> >> diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/controller/pcie-brcmstb.c >> index 50607df34a66..03396a9d97be 100644 >> --- a/drivers/pci/controller/pcie-brcmstb.c >> +++ b/drivers/pci/controller/pcie-brcmstb.c >> @@ -55,6 +55,10 @@ >> #define PCIE_RC_DL_MDIO_WR_DATA 0x1104 >> #define PCIE_RC_DL_MDIO_RD_DATA 0x1108 >> >> +#define PCIE_RC_PL_PHY_CTL_15 0x184c >> +#define PCIE_RC_PL_PHY_CTL_15_DIS_PLL_PD_MASK 0x400000 >> +#define PCIE_RC_PL_PHY_CTL_15_PM_CLK_PERIOD_MASK 0xff >> + >> #define PCIE_MISC_MISC_CTRL 0x4008 >> #define PCIE_MISC_MISC_CTRL_PCIE_RCB_64B_MODE_MASK 0x80 >> #define PCIE_MISC_MISC_CTRL_PCIE_RCB_MPS_MODE_MASK 0x400 >> @@ -251,6 +255,7 @@ struct pcie_cfg_data { >> u8 num_inbound_wins; >> int (*perst_set)(struct brcm_pcie *pcie, u32 val); >> int (*bridge_sw_init_set)(struct brcm_pcie *pcie, u32 val); >> + int (*post_setup)(struct brcm_pcie *pcie); >> }; >> >> struct subdev_regulators { >> @@ -826,6 +831,38 @@ static int brcm_pcie_perst_set_generic(struct brcm_pcie *pcie, u32 val) >> return 0; >> } >> >> +static int brcm_pcie_post_setup_bcm2712(struct brcm_pcie *pcie) >> +{ >> + const u16 data[] = { 0x50b9, 0xbda1, 0x0094, 0x97b4, 0x5030, 0x5030, 0x0007 }; >> + const u8 regs[] = { 0x16, 0x17, 0x18, 0x19, 0x1b, 0x1c, 0x1e }; >> + int ret, i; >> + u32 tmp; >> + >> + /* Allow a 54MHz (xosc) refclk source */ >> + ret = brcm_pcie_mdio_write(pcie->base, MDIO_PORT0, SET_ADDR_OFFSET, 0x1600); >> + if (ret < 0) >> + return ret; >> + >> + for (i = 0; i < ARRAY_SIZE(regs); i++) { >> + ret = brcm_pcie_mdio_write(pcie->base, MDIO_PORT0, regs[i], data[i]); >> + if (ret < 0) >> + return ret; >> + } >> + >> + usleep_range(100, 200); >> + >> + /* >> + * Set L1SS sub-state timers to avoid lengthy state transitions, >> + * PM clock period is 18.52ns (1/54MHz, round down). >> + */ >> + tmp = readl(pcie->base + PCIE_RC_PL_PHY_CTL_15); >> + tmp &= ~PCIE_RC_PL_PHY_CTL_15_PM_CLK_PERIOD_MASK; >> + tmp |= 0x12; >> + writel(tmp, pcie->base + PCIE_RC_PL_PHY_CTL_15); >> + >> + return 0; >> +} >> + >> static void add_inbound_win(struct inbound_win *b, u8 *count, u64 size, >> u64 cpu_addr, u64 pci_offset) >> { >> @@ -1189,6 +1226,12 @@ static int brcm_pcie_setup(struct brcm_pcie *pcie) >> PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR2_MASK); >> writel(tmp, base + PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1); >> >> + if (pcie->cfg->post_setup) { >> + ret = pcie->cfg->post_setup(pcie); >> + if (ret < 0) >> + return ret; >> + } >> + >> return 0; >> } >> >> @@ -1715,6 +1758,7 @@ static const struct pcie_cfg_data bcm2712_cfg = { >> .soc_base = BCM7712, >> .perst_set = brcm_pcie_perst_set_7278, >> .bridge_sw_init_set = brcm_pcie_bridge_sw_init_set_generic, >> + .post_setup = brcm_pcie_post_setup_bcm2712, >> .quirks = CFG_QUIRK_AVOID_BRIDGE_SHUTDOWN, >> .num_inbound_wins = 10, >> }; >> -- >> 2.47.0 >> > Hi Stan, > Any reason you didn't make this a quirk like the other commit? Not a special reason. I think that the code is more readable with separate ops function which is executed after the generic .setup function. The other SoC/variants could also benefit of such op. > Reviewed-by: Jim Quinlan <james.quinlan@broadcom.com> Thanks! ~Stan
diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/controller/pcie-brcmstb.c index 50607df34a66..03396a9d97be 100644 --- a/drivers/pci/controller/pcie-brcmstb.c +++ b/drivers/pci/controller/pcie-brcmstb.c @@ -55,6 +55,10 @@ #define PCIE_RC_DL_MDIO_WR_DATA 0x1104 #define PCIE_RC_DL_MDIO_RD_DATA 0x1108 +#define PCIE_RC_PL_PHY_CTL_15 0x184c +#define PCIE_RC_PL_PHY_CTL_15_DIS_PLL_PD_MASK 0x400000 +#define PCIE_RC_PL_PHY_CTL_15_PM_CLK_PERIOD_MASK 0xff + #define PCIE_MISC_MISC_CTRL 0x4008 #define PCIE_MISC_MISC_CTRL_PCIE_RCB_64B_MODE_MASK 0x80 #define PCIE_MISC_MISC_CTRL_PCIE_RCB_MPS_MODE_MASK 0x400 @@ -251,6 +255,7 @@ struct pcie_cfg_data { u8 num_inbound_wins; int (*perst_set)(struct brcm_pcie *pcie, u32 val); int (*bridge_sw_init_set)(struct brcm_pcie *pcie, u32 val); + int (*post_setup)(struct brcm_pcie *pcie); }; struct subdev_regulators { @@ -826,6 +831,38 @@ static int brcm_pcie_perst_set_generic(struct brcm_pcie *pcie, u32 val) return 0; } +static int brcm_pcie_post_setup_bcm2712(struct brcm_pcie *pcie) +{ + const u16 data[] = { 0x50b9, 0xbda1, 0x0094, 0x97b4, 0x5030, 0x5030, 0x0007 }; + const u8 regs[] = { 0x16, 0x17, 0x18, 0x19, 0x1b, 0x1c, 0x1e }; + int ret, i; + u32 tmp; + + /* Allow a 54MHz (xosc) refclk source */ + ret = brcm_pcie_mdio_write(pcie->base, MDIO_PORT0, SET_ADDR_OFFSET, 0x1600); + if (ret < 0) + return ret; + + for (i = 0; i < ARRAY_SIZE(regs); i++) { + ret = brcm_pcie_mdio_write(pcie->base, MDIO_PORT0, regs[i], data[i]); + if (ret < 0) + return ret; + } + + usleep_range(100, 200); + + /* + * Set L1SS sub-state timers to avoid lengthy state transitions, + * PM clock period is 18.52ns (1/54MHz, round down). + */ + tmp = readl(pcie->base + PCIE_RC_PL_PHY_CTL_15); + tmp &= ~PCIE_RC_PL_PHY_CTL_15_PM_CLK_PERIOD_MASK; + tmp |= 0x12; + writel(tmp, pcie->base + PCIE_RC_PL_PHY_CTL_15); + + return 0; +} + static void add_inbound_win(struct inbound_win *b, u8 *count, u64 size, u64 cpu_addr, u64 pci_offset) { @@ -1189,6 +1226,12 @@ static int brcm_pcie_setup(struct brcm_pcie *pcie) PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR2_MASK); writel(tmp, base + PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1); + if (pcie->cfg->post_setup) { + ret = pcie->cfg->post_setup(pcie); + if (ret < 0) + return ret; + } + return 0; } @@ -1715,6 +1758,7 @@ static const struct pcie_cfg_data bcm2712_cfg = { .soc_base = BCM7712, .perst_set = brcm_pcie_perst_set_7278, .bridge_sw_init_set = brcm_pcie_bridge_sw_init_set_generic, + .post_setup = brcm_pcie_post_setup_bcm2712, .quirks = CFG_QUIRK_AVOID_BRIDGE_SHUTDOWN, .num_inbound_wins = 10, };