| Message ID | 20250127221631.3974583-3-jm@ti.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | Add R5F and C7xv device nodes | expand |
On 1/27/25 4:16 PM, Judith Mendez wrote: > From: Hari Nagalla <hnagalla@ti.com> > > AM62A SoCs have a single R5F core in the MCU voltage domain. The MCU > domain also has a 512KB sram memory, the R5F core can use for > applications needing fast memory access. > > Signed-off-by: Hari Nagalla <hnagalla@ti.com> > [Judith: Fix commit message header] > Signed-off-by: Judith Mendez <jm@ti.com> > --- > arch/arm64/boot/dts/ti/k3-am62a-mcu.dtsi | 36 ++++++++++++++++++++++++ > 1 file changed, 36 insertions(+) > > diff --git a/arch/arm64/boot/dts/ti/k3-am62a-mcu.dtsi b/arch/arm64/boot/dts/ti/k3-am62a-mcu.dtsi > index 0469c766b769e..9a20f75e48063 100644 > --- a/arch/arm64/boot/dts/ti/k3-am62a-mcu.dtsi > +++ b/arch/arm64/boot/dts/ti/k3-am62a-mcu.dtsi > @@ -6,6 +6,18 @@ > */ > > &cbass_mcu { > + mcu_ram: sram@79100000 { > + compatible = "mmio-sram"; > + reg = <0x00 0x79100000 0x00 0x80000>; > + ranges = <0x00 0x00 0x79100000 0x80000>; > + #address-cells = <1>; > + #size-cells = <1>; > + > + mcu1-sram@0 { > + reg = <0x0 0x80000>; > + }; > + }; > + > mcu_pmx0: pinctrl@4084000 { > compatible = "pinctrl-single"; > reg = <0x00 0x04084000 0x00 0x88>; > @@ -175,4 +187,28 @@ mcu_mcan1: can@4e18000 { > bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; > status = "disabled"; > }; > + > + mcu_r5fss0: r5fss@79000000 { > + compatible = "ti,am62-r5fss"; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0x79000000 0x00 0x79000000 0x8000>, > + <0x79020000 0x00 0x79020000 0x8000>; > + power-domains = <&k3_pds 7 TI_SCI_PD_EXCLUSIVE>; Newline here. Also this should be default "disabled". It can be set to "okay" in the board DTS file when the needed mboxes and memory-region are set. Speaking of that, where are those patches? This is incomplete without them and these nodes will not function. Same for the DSP patch. Andrew > + mcu_r5fss0_core0: r5f@79000000 { > + compatible = "ti,am62-r5f"; > + reg = <0x79000000 0x00008000>, > + <0x79020000 0x00008000>; > + reg-names = "atcm", "btcm"; > + ti,sci = <&dmsc>; > + ti,sci-dev-id = <9>; > + ti,sci-proc-ids = <0x03 0xff>; > + resets = <&k3_reset 9 1>; > + firmware-name = "am62a-mcu-r5f0_0-fw"; > + ti,atcm-enable = <0>; > + ti,btcm-enable = <1>; > + ti,loczrama = <0>; > + sram = <&mcu_ram>; > + }; > + }; > };
On 1/28/25 10:27, Andrew Davis wrote: >> + mcu_r5fss0: r5fss@79000000 { >> + compatible = "ti,am62-r5fss"; >> + #address-cells = <1>; >> + #size-cells = <1>; >> + ranges = <0x79000000 0x00 0x79000000 0x8000>, >> + <0x79020000 0x00 0x79020000 0x8000>; >> + power-domains = <&k3_pds 7 TI_SCI_PD_EXCLUSIVE>; > > Newline here. > > Also this should be default "disabled". It can be set to "okay" > in the board DTS file when the needed mboxes and memory-region > are set. Speaking of that, where are those patches? This is > incomplete without them and these nodes will not function. > Same for the DSP patch. > > Andrew Yes, by default needs to set the node state to "disabled". This is HW description of the wake-up domain components. Memory carve outs and mailbox assignments for IPC are a separate patch as it is configurable and distro dependent.
Hi Andrew, On 1/28/25 10:52 AM, Hari Nagalla wrote: > On 1/28/25 10:27, Andrew Davis wrote: >>> + mcu_r5fss0: r5fss@79000000 { >>> + compatible = "ti,am62-r5fss"; >>> + #address-cells = <1>; >>> + #size-cells = <1>; >>> + ranges = <0x79000000 0x00 0x79000000 0x8000>, >>> + <0x79020000 0x00 0x79020000 0x8000>; >>> + power-domains = <&k3_pds 7 TI_SCI_PD_EXCLUSIVE>; >> >> Newline here. >> >> Also this should be default "disabled". It can be set to "okay" >> in the board DTS file when the needed mboxes and memory-region >> are set. Speaking of that, where are those patches? This is >> incomplete without them and these nodes will not function. >> Same for the DSP patch. >> >> Andrew > Yes, by default needs to set the node state to "disabled". This is HW > description of the wake-up domain components. Memory carve outs and > mailbox assignments for IPC are a separate patch as it is configurable > and distro dependent. Yes I plan to disable the nodes in each domain .dtsi file. Also yes, my understanding is that the memory carveouts could be a separate series if at all. Not sure if those patches can be sent upstream since they are distro dependent. Can anyone clarify if this is the case? ~ Judith
On 1/28/25 11:48 AM, Judith Mendez wrote: > Hi Andrew, > > On 1/28/25 10:52 AM, Hari Nagalla wrote: >> On 1/28/25 10:27, Andrew Davis wrote: >>>> + mcu_r5fss0: r5fss@79000000 { >>>> + compatible = "ti,am62-r5fss"; >>>> + #address-cells = <1>; >>>> + #size-cells = <1>; >>>> + ranges = <0x79000000 0x00 0x79000000 0x8000>, >>>> + <0x79020000 0x00 0x79020000 0x8000>; >>>> + power-domains = <&k3_pds 7 TI_SCI_PD_EXCLUSIVE>; >>> >>> Newline here. >>> >>> Also this should be default "disabled". It can be set to "okay" >>> in the board DTS file when the needed mboxes and memory-region >>> are set. Speaking of that, where are those patches? This is >>> incomplete without them and these nodes will not function. >>> Same for the DSP patch. >>> >>> Andrew >> Yes, by default needs to set the node state to "disabled". This is HW >> description of the wake-up domain components. Memory carve outs and >> mailbox assignments for IPC are a separate patch as it is configurable >> and distro dependent. > > Yes I plan to disable the nodes in each domain .dtsi file. > > Also yes, my understanding is that the memory carveouts could > be a separate series if at all. Not sure if those patches can be > sent upstream since they are distro dependent. Can anyone clarify > if this is the case? > As per offline discussion, I will include the memory carveouts in this same series. ~ Judith > ~ Judith >
diff --git a/arch/arm64/boot/dts/ti/k3-am62a-mcu.dtsi b/arch/arm64/boot/dts/ti/k3-am62a-mcu.dtsi index 0469c766b769e..9a20f75e48063 100644 --- a/arch/arm64/boot/dts/ti/k3-am62a-mcu.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62a-mcu.dtsi @@ -6,6 +6,18 @@ */ &cbass_mcu { + mcu_ram: sram@79100000 { + compatible = "mmio-sram"; + reg = <0x00 0x79100000 0x00 0x80000>; + ranges = <0x00 0x00 0x79100000 0x80000>; + #address-cells = <1>; + #size-cells = <1>; + + mcu1-sram@0 { + reg = <0x0 0x80000>; + }; + }; + mcu_pmx0: pinctrl@4084000 { compatible = "pinctrl-single"; reg = <0x00 0x04084000 0x00 0x88>; @@ -175,4 +187,28 @@ mcu_mcan1: can@4e18000 { bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; status = "disabled"; }; + + mcu_r5fss0: r5fss@79000000 { + compatible = "ti,am62-r5fss"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x79000000 0x00 0x79000000 0x8000>, + <0x79020000 0x00 0x79020000 0x8000>; + power-domains = <&k3_pds 7 TI_SCI_PD_EXCLUSIVE>; + mcu_r5fss0_core0: r5f@79000000 { + compatible = "ti,am62-r5f"; + reg = <0x79000000 0x00008000>, + <0x79020000 0x00008000>; + reg-names = "atcm", "btcm"; + ti,sci = <&dmsc>; + ti,sci-dev-id = <9>; + ti,sci-proc-ids = <0x03 0xff>; + resets = <&k3_reset 9 1>; + firmware-name = "am62a-mcu-r5f0_0-fw"; + ti,atcm-enable = <0>; + ti,btcm-enable = <1>; + ti,loczrama = <0>; + sram = <&mcu_ram>; + }; + }; };