| Message ID | 20250207083616.1442887-10-alexander.stein@ew.tq-group.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | Make i.MX8M OCOTP work as accessing controller | expand |
On Fri, Feb 07, 2025 at 09:36:14AM +0100, Alexander Stein wrote: > These definitions define the location of corresponding disable bits > in OCOTP peripheral. > > Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com> > --- Reviewed-by: Frank Li <Frank.Li@nxp.com> > arch/arm64/boot/dts/freescale/imx8mq-ocotp.h | 37 ++++++++++++++++++++ > 1 file changed, 37 insertions(+) > create mode 100644 arch/arm64/boot/dts/freescale/imx8mq-ocotp.h > > diff --git a/arch/arm64/boot/dts/freescale/imx8mq-ocotp.h b/arch/arm64/boot/dts/freescale/imx8mq-ocotp.h > new file mode 100644 > index 0000000000000..d991d57816264 > --- /dev/null > +++ b/arch/arm64/boot/dts/freescale/imx8mq-ocotp.h > @@ -0,0 +1,37 @@ > +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) > +/* > + * Copyright (c) 2025 TQ-Systems GmbH <linux@ew.tq-group.com>, > + * D-82229 Seefeld, Germany. > + * Author: Alexander Stein > + */ > + > +#ifndef __DTS_IMX8MQ_OCOTP_H > +#define __DTS_IMX8MQ_OCOTP_H > + > +/* > + * The OCOTP is a tuple of > + * <fuse_addr fuse_bit_offset> > + */ > + > +#define IMX8MQ_OCOTP_M4_DISABLE 20 8 > +#define IMX8MQ_OCOTP_M4_MPU_DISABLE 20 9 > +#define IMX8MQ_OCOTP_M4_FPU_DISABLE 20 10 > +#define IMX8MQ_OCOTP_USB_OTG1_DISABLE 20 11 > +#define IMX8MQ_OCOTP_USB_OTG2_DISABLE 20 12 > +#define IMX8MQ_OCOTP_DOLBY_DISABLE 20 13 > +#define IMX8MQ_OCOTP_VP9_DISABLE 20 18 > +#define IMX8MQ_OCOTP_HEVC_DISABLE 20 19 > +#define IMX8MQ_OCOTP_AVC_DISABLE 20 20 > +#define IMX8MQ_OCOTP_VPU_DISABLE 20 21 > +#define IMX8MQ_OCOTP_PCIE1_DISABLE 20 22 > +#define IMX8MQ_OCOTP_PCIE2_DISABLE 20 23 > +#define IMX8MQ_OCOTP_GPU_DISABLE 20 24 > +#define IMX8MQ_OCOTP_HDMI_DISABLE 20 25 > +#define IMX8MQ_OCOTP_DC_DISABLE 20 26 > +#define IMX8MQ_OCOTP_HDCP_DISABLE 20 27 > +#define IMX8MQ_OCOTP_MIPI_DSI_DISABLE 20 28 > +#define IMX8MQ_OCOTP_ENET_DISABLE 20 29 > +#define IMX8MQ_OCOTP_MIPI_CSI1_DISABLE 20 30 > +#define IMX8MQ_OCOTP_MIPI_CSI2_DISABLE 20 31 > + > +#endif /* __DTS_IMX8MQ_OCOTP_H */ > -- > 2.34.1 >
diff --git a/arch/arm64/boot/dts/freescale/imx8mq-ocotp.h b/arch/arm64/boot/dts/freescale/imx8mq-ocotp.h new file mode 100644 index 0000000000000..d991d57816264 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mq-ocotp.h @@ -0,0 +1,37 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright (c) 2025 TQ-Systems GmbH <linux@ew.tq-group.com>, + * D-82229 Seefeld, Germany. + * Author: Alexander Stein + */ + +#ifndef __DTS_IMX8MQ_OCOTP_H +#define __DTS_IMX8MQ_OCOTP_H + +/* + * The OCOTP is a tuple of + * <fuse_addr fuse_bit_offset> + */ + +#define IMX8MQ_OCOTP_M4_DISABLE 20 8 +#define IMX8MQ_OCOTP_M4_MPU_DISABLE 20 9 +#define IMX8MQ_OCOTP_M4_FPU_DISABLE 20 10 +#define IMX8MQ_OCOTP_USB_OTG1_DISABLE 20 11 +#define IMX8MQ_OCOTP_USB_OTG2_DISABLE 20 12 +#define IMX8MQ_OCOTP_DOLBY_DISABLE 20 13 +#define IMX8MQ_OCOTP_VP9_DISABLE 20 18 +#define IMX8MQ_OCOTP_HEVC_DISABLE 20 19 +#define IMX8MQ_OCOTP_AVC_DISABLE 20 20 +#define IMX8MQ_OCOTP_VPU_DISABLE 20 21 +#define IMX8MQ_OCOTP_PCIE1_DISABLE 20 22 +#define IMX8MQ_OCOTP_PCIE2_DISABLE 20 23 +#define IMX8MQ_OCOTP_GPU_DISABLE 20 24 +#define IMX8MQ_OCOTP_HDMI_DISABLE 20 25 +#define IMX8MQ_OCOTP_DC_DISABLE 20 26 +#define IMX8MQ_OCOTP_HDCP_DISABLE 20 27 +#define IMX8MQ_OCOTP_MIPI_DSI_DISABLE 20 28 +#define IMX8MQ_OCOTP_ENET_DISABLE 20 29 +#define IMX8MQ_OCOTP_MIPI_CSI1_DISABLE 20 30 +#define IMX8MQ_OCOTP_MIPI_CSI2_DISABLE 20 31 + +#endif /* __DTS_IMX8MQ_OCOTP_H */
These definitions define the location of corresponding disable bits in OCOTP peripheral. Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com> --- arch/arm64/boot/dts/freescale/imx8mq-ocotp.h | 37 ++++++++++++++++++++ 1 file changed, 37 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8mq-ocotp.h