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Tue, 11 Feb 2025 12:21:39 -0600 From: Chintan Vankar To: Conor Dooley , Krzysztof Kozlowski , Rob Herring , Tero Kristo , Vignesh Raghavendra , Nishanth Menon CC: , , , , , , Chintan Vankar , Ravi Gunasekaran Subject: [PATCH v4 2/2] arm64: dts: ti: k3-am62a7: Add overlay for second CPSW3G Port Date: Tue, 11 Feb 2025 23:51:34 +0530 Message-ID: <20250211182134.1500867-3-c-vankar@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250211182134.1500867-1-c-vankar@ti.com> References: <20250211182134.1500867-1-c-vankar@ti.com> MIME-Version: 1.0 X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250211_182152_346966_C32C3F6B X-CRM114-Status: GOOD ( 14.27 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Siddharth Vadapalli The SK-Ethernet-DC01 Add-On Ethernet Card for AM62A7-SK board supports RGMII mode. Add overlay to enable the second CPSW3G port in RGMII-RXID mode with the Add-On Ethernet Card. Signed-off-by: Siddharth Vadapalli Signed-off-by: Chintan Vankar Reviewed-by: Ravi Gunasekaran --- Link to v3: https://lore.kernel.org/r/20240429101739.2770090-3-c-vankar@ti.com/ Changes from v3 to v4: - No changes. arch/arm64/boot/dts/ti/Makefile | 3 + .../dts/ti/k3-am62a7-sk-ethernet-dc01.dtso | 62 +++++++++++++++++++ 2 files changed, 65 insertions(+) create mode 100644 arch/arm64/boot/dts/ti/k3-am62a7-sk-ethernet-dc01.dtso diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile index 8a4bdf87e2d4..7f9f0d3b9362 100644 --- a/arch/arm64/boot/dts/ti/Makefile +++ b/arch/arm64/boot/dts/ti/Makefile @@ -31,6 +31,7 @@ dtb-$(CONFIG_ARCH_K3) += k3-am62-lp-sk-nand.dtbo # Boards with AM62Ax SoC dtb-$(CONFIG_ARCH_K3) += k3-am62a7-sk.dtb dtb-$(CONFIG_ARCH_K3) += k3-am62a7-phyboard-lyra-rdk.dtb +dtb-$(CONFIG_ARCH_K3) += k3-am62a7-sk-ethernet-dc01.dtbo # Boards with AM62Px SoC dtb-$(CONFIG_ARCH_K3) += k3-am62p5-sk.dtb @@ -160,6 +161,8 @@ k3-am62a7-sk-csi2-ov5640-dtbs := k3-am62a7-sk.dtb \ k3-am62x-sk-csi2-ov5640.dtbo k3-am62a7-sk-csi2-tevi-ov5640-dtbs := k3-am62a7-sk.dtb \ k3-am62x-sk-csi2-tevi-ov5640.dtbo +k3-am62a7-sk-ethernet-dc01-dtbs := k3-am62a7-sk.dtb \ + k3-am62a7-sk-ethernet-dc01.dtbo k3-am62a7-sk-hdmi-audio-dtbs := k3-am62a7-sk.dtb k3-am62x-sk-hdmi-audio.dtbo k3-am62p5-sk-csi2-imx219-dtbs := k3-am62p5-sk.dtb \ k3-am62x-sk-csi2-imx219.dtbo diff --git a/arch/arm64/boot/dts/ti/k3-am62a7-sk-ethernet-dc01.dtso b/arch/arm64/boot/dts/ti/k3-am62a7-sk-ethernet-dc01.dtso new file mode 100644 index 000000000000..b06362de6642 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am62a7-sk-ethernet-dc01.dtso @@ -0,0 +1,62 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/** + * DT Overlay for second CPSW3G port in RGMII mode using SK-ETHERNET-DC01 + * Add-On Daughtercard with AM62A7-SK. + * + * Copyright (C) 2024-2025 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include "k3-pinctrl.h" + +&{/} { + aliases { + ethernet1 = "/bus@f0000/ethernet@8000000/ethernet-ports/port@2"; + }; +}; + +&cpsw3g { + pinctrl-0 = <&main_rgmii1_pins_default>, + <&main_rgmii2_pins_default>; +}; + +&cpsw_port2 { + status = "okay"; + phy-mode = "rgmii-rxid"; + phy-handle = <&cpsw3g_phy1>; +}; + +&cpsw3g_mdio { + #address-cells = <1>; + #size-cells = <0>; + + cpsw3g_phy1: ethernet-phy@1 { + reg = <1>; + ti,rx-internal-delay = ; + ti,fifo-depth = ; + ti,min-output-impedance; + }; +}; + +&main_pmx0 { + main_rgmii2_pins_default: main-rgmii2-default-pins { + pinctrl-single,pins = < + AM62AX_IOPAD(0x0184, PIN_INPUT, 0) /* (AA21) RGMII2_RD0 */ + AM62AX_IOPAD(0x0188, PIN_INPUT, 0) /* (Y20) RGMII2_RD1 */ + AM62AX_IOPAD(0x018c, PIN_INPUT, 0) /* (AB21) RGMII2_RD2 */ + AM62AX_IOPAD(0x0190, PIN_INPUT, 0) /* (AB20) RGMII2_RD3 */ + AM62AX_IOPAD(0x0180, PIN_INPUT, 0) /* (AA20) RGMII2_RXC */ + AM62AX_IOPAD(0x017c, PIN_INPUT, 0) /* (W18) RGMII2_RX_CTL */ + AM62AX_IOPAD(0x016c, PIN_INPUT, 0) /* (AA19) RGMII2_TD0 */ + AM62AX_IOPAD(0x0170, PIN_INPUT, 0) /* (Y18) RGMII2_TD1 */ + AM62AX_IOPAD(0x0174, PIN_INPUT, 0) /* (AA18) RGMII2_TD2 */ + AM62AX_IOPAD(0x0178, PIN_INPUT, 0) /* (W17) RGMII2_TD3 */ + AM62AX_IOPAD(0x0168, PIN_INPUT, 0) /* (AB19) RGMII2_TXC */ + AM62AX_IOPAD(0x0164, PIN_INPUT, 0) /* (Y19) RGMII2_TX_CTL */ + >; + }; +};