From patchwork Tue Feb 11 16:07:31 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nick Chan X-Patchwork-Id: 13970108 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A8267C0219B for ; Tue, 11 Feb 2025 16:25:04 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Cc:To:In-Reply-To:References :Message-Id:Content-Transfer-Encoding:Content-Type:MIME-Version:Subject:Date: From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=1O3DPqsHMZl+tQK8e6H66+oY0Dkf1V6lPtG345WzuQw=; b=vhfIdx52U6YXE+DbVRXpIwaNME Q4bRztd6m9ltnnAjeQzfpvfVFDRSlECPHdXsOEt6K7+wSJGlXzYMJfOI5LflsFPOD24D9Hcvx7ye7 yzTWba+Iyhh/G3sieKdrGMH1I/a03Rzzcb0c1TZZEL+jaMCLypL0gkOZhkdsfAo2uhjT9t72bgUF9 vd4E0EGonaOPTErdWR6Simzmmw7at5QViac7rdhgkuv2OZustFNsc40Xgdwqe4icUt5ql2AmWTsz/ NUJ2h8THSe8E9K1qjwEXyyFp8L70wq4Rj8trCRLKSHGLKj4kom2wNGk1kMzxcpP60WXPBUWFL1KEH VqCvV4oA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1tht4B-00000004UZ7-493A; Tue, 11 Feb 2025 16:24:55 +0000 Received: from mail-pj1-x1029.google.com ([2607:f8b0:4864:20::1029]) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1thsoV-00000004QYf-167x for linux-arm-kernel@lists.infradead.org; Tue, 11 Feb 2025 16:08:44 +0000 Received: by mail-pj1-x1029.google.com with SMTP id 98e67ed59e1d1-2f9b91dff71so8866642a91.2 for ; Tue, 11 Feb 2025 08:08:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1739290123; x=1739894923; darn=lists.infradead.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=1O3DPqsHMZl+tQK8e6H66+oY0Dkf1V6lPtG345WzuQw=; b=izPi9FQw2ypcvJJt5OngdG1dQ76Zud08BuQz7RzH/iFvzLi2xu94fHppogbwOZegmT qjTNqSHYMKAtuwgX4X2AroNh2mHSl7snllJu5jlMT8FuOlXqI8Vmwrr1CBf6EqHmhixR 9FfMhlopoZwuZbDhoztm5DIw/NYYfCaURD3pG8fG24vknjeNZs8pKeLGZgBaj0izIOw8 sNwYi2lfg+Vep2cLQ8LThDwqbNqSc8wPagGT0nmpir6ya6HyAX5mv1bAVFfoq3Qc1zam t8JZ9w7jAnPp5aFnuDfNd2e2cVTQpnrc7kZTw8DE6NKyZFe68TlcyuSDa4M6d8zOjWa+ 7Avw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1739290123; x=1739894923; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=1O3DPqsHMZl+tQK8e6H66+oY0Dkf1V6lPtG345WzuQw=; b=rgowjIrXzrWcYICEO4UG11wkJ4u+GkwxhHDyzD77sUoVYbPiJSyyZap7ddYz/8EfJK YufC19cSWr7pVdnc+kkEIlhAuspAN0kKJY8SiSOnnVRrcm+Nfuc8cgs5r2fOuz5XLmj2 YuLCQS4ekbxzJI+N1CziZ+D68MxkQZKuA3/mRFeT/1Sezh+JUVWHeL5oFZDMhqRhq92j oagLL3kcLlqW30es+85m4a2Vc1qXuyntqQRG4uuY+EitoRwG4VIcnVUpZgia0QRZ9A/8 Hbq6dGIORaQPD8IMUBMzKGCao4MvXQ8kRJpfdcctGViUg/kjFiwZ6tVlHKMDIT6JVFv8 R+UA== X-Forwarded-Encrypted: i=1; AJvYcCU1ImuZMm9mUJ/vxI4UTw7McXXBaHNxzEXlOySfRjyuUo0dg0N6QlJerGnOd2PXifgJqNxa8ZIHjlUKqd8pjOPW@lists.infradead.org X-Gm-Message-State: AOJu0YwoPjw2bovgKAFxnu3am+5GE4cj+Qc3axOR+qWdwchNZZu2sDN9 kO1/FIYevDfk/yqczQ7sd5guZDpXZ6n/SXFdvU6BZyMt0o2n7NRC X-Gm-Gg: ASbGnctrreQwzngdy03j/DmmTHORBFB9S/dw7cXE6W5/7rlKfTvvyHeOeE0dxHtX+BF +FwkieSQKTzzsDM9YwBHsq0s4qGWzZEgLuUKPSu2TcIfY8roQZZRxCI2wvha1ER1uPLv8JRv+Na f0s0YjxoiChbhK0QgTCLF3vPXz7KtAQfi/gCy07E2338/y7Xr+bZQcMVmV8/9AHqIjtU6fRIURG yyv6cmbw0Cgzyj6DACEqjgUlJI+GI55K13ubBmJ1HyqCtC62oWXxyuoNYb9sTXz8Bo9Vcr3uZji oyUtgklPqB2VFxEXrw== X-Google-Smtp-Source: AGHT+IG6G7065tb9vEJwgv5bPL6BKiPdWBuG/Hrx2vDGxQYdRxxeXQT5pT1jbB1l2NApBuR0T5Sp8A== X-Received: by 2002:a17:90b:368c:b0:2ee:741c:e9f4 with SMTP id 98e67ed59e1d1-2fa2406434fmr26864538a91.11.1739290122639; Tue, 11 Feb 2025 08:08:42 -0800 (PST) Received: from [127.0.1.1] ([59.188.211.160]) by smtp.googlemail.com with ESMTPSA id 98e67ed59e1d1-2fa618e5e18sm6040478a91.41.2025.02.11.08.08.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Feb 2025 08:08:42 -0800 (PST) From: Nick Chan Date: Wed, 12 Feb 2025 00:07:31 +0800 Subject: [PATCH 10/10] drivers/perf: apple_m1: Add Apple A11 Support MIME-Version: 1.0 Message-Id: <20250212-apple-cpmu-v1-10-f8c7f2ac1743@gmail.com> References: <20250212-apple-cpmu-v1-0-f8c7f2ac1743@gmail.com> In-Reply-To: <20250212-apple-cpmu-v1-0-f8c7f2ac1743@gmail.com> To: Will Deacon , Mark Rutland , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Catalin Marinas Cc: Marc Zyngier , linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org, devicetree@vger.kernel.org, asahi@lists.linux.dev, linux-kernel@vger.kernel.org, Nick Chan X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=7901; i=towinchenmi@gmail.com; h=from:subject:message-id; bh=rwHc3mgKnwMYwfhwpQDSG8cR6N18yvZFC8tKzaeZXoU=; b=owEBbQKS/ZANAwAIAQHKCLemxQgkAcsmYgBnq3XoE+tpQdF4eMnLpXXSfA/45LMt+MPF4PryP HMKAvOU+oyJAjMEAAEIAB0WIQRLUnh4XJes95w8aIMBygi3psUIJAUCZ6t16AAKCRABygi3psUI JDY4D/9BWdJs7RseCRXasa64BXCmII0mEHmATtqN/ryxrmoM6+thpTRt+TYis+1ZMfyZFrZO2E/ YzDHsBIuIbaHPUbKhL1BfhzGmqO7CpZmWxGkuf7PyjOey8Q0zoHJQwRgflhFQ2fFBc3q13L0wLf mfjfCCq9mylKTKkFtW+4Fcy7QQ7Ho5MFP0PJbKzQyVzbtXAqc3ERyjND5KFV70nNiLxUjlcMHVy PrVhGvdXNv9lhVSHHhNiOn76jRyeBWwZXkgbGtbC4QcGepkuxfSfyWCfu7baOvMwhMhKXpSxHGm lAM7NrDqMaaoHpBbuaHADTd3l7GtyOOjzEoc28R9EAhi4gaeMMyB+1Pi207tN+OZ/ww8XyDnSy+ UXdr8Klbt7b2+6pUqoxHVOoAz1AaQRXr92/rZ7eg4lJZdwSj9sQGWLWXA4P+2ydkhusYrl3UgWW f6Dsm+BUPQFelMaRnrdgEQUlwZJR+blt1rxScdhVsAQ6MLEgNfY5363XI6sdpfVF5m1MStpJ6lw RoI0lNYOGjYVHMs7kmpudj5lZXY9SewGr4NXUPU4xl47AVLPmWViXzBak3XaC/0fItmszqIaXAe XeIC3ST2zdkVhfu07ZhDLQjeeey2xJwW7hdUUBK+caxyTazdFgiv7iruP9UrH8FGetGUODlcZUP 6p+3aKqjx8qtpYw== X-Developer-Key: i=towinchenmi@gmail.com; a=openpgp; fpr=4B5278785C97ACF79C3C688301CA08B7A6C50824 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250211_080843_306448_762ED677 X-CRM114-Status: GOOD ( 13.39 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add support for the CPU PMU found attached to the performance and efficiency cores of the Apple A11 SoCs. This PMU can deliver its interrupt via IRQ or FIQ. Use FIQ as that is faster. Signed-off-by: Nick Chan --- drivers/perf/apple_m1_cpu_pmu.c | 135 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 135 insertions(+) diff --git a/drivers/perf/apple_m1_cpu_pmu.c b/drivers/perf/apple_m1_cpu_pmu.c index 2eafcb1bfcf6bf4b57a939c5470552cba81e7758..254eb8e08906c2f0366c27f2089095ecd2fc7adb 100644 --- a/drivers/perf/apple_m1_cpu_pmu.c +++ b/drivers/perf/apple_m1_cpu_pmu.c @@ -500,6 +500,113 @@ static const u16 a10_pmu_event_affinity[A10_PMU_PERFCTR_LAST + 1] = { [A10_PMU_PERFCTR_UNKNOWN_fd] = ONLY_2_4_6, }; +enum a11_pmu_events { + A11_PMU_PERFCTR_RETIRE_UOP = 0x1, + A11_PMU_PERFCTR_CORE_ACTIVE_CYCLE = 0x2, + A11_PMU_PERFCTR_L2_TLB_MISS_INSTRUCTION = 0xa, + A11_PMU_PERFCTR_L2_TLB_MISS_DATA = 0xb, + A11_PMU_PERFCTR_SCHEDULE_UOP = 0x52, + A11_PMU_PERFCTR_MAP_REWIND = 0x75, + A11_PMU_PERFCTR_MAP_STALL = 0x76, + A11_PMU_PERFCTR_MAP_INT_UOP = 0x7c, + A11_PMU_PERFCTR_MAP_LDST_UOP = 0x7d, + A11_PMU_PERFCTR_MAP_SIMD_UOP = 0x7e, + A11_PMU_PERFCTR_FLUSH_RESTART_OTHER_NONSPEC = 0x84, + A11_PMU_PERFCTR_INST_A32 = 0x8a, + A11_PMU_PERFCTR_INST_T32 = 0x8b, + A11_PMU_PERFCTR_INST_ALL = 0x8c, + A11_PMU_PERFCTR_INST_BRANCH = 0x8d, + A11_PMU_PERFCTR_INST_BRANCH_CALL = 0x8e, + A11_PMU_PERFCTR_INST_BRANCH_RET = 0x8f, + A11_PMU_PERFCTR_INST_BRANCH_TAKEN = 0x90, + A11_PMU_PERFCTR_INST_BRANCH_INDIR = 0x93, + A11_PMU_PERFCTR_INST_BRANCH_COND = 0x94, + A11_PMU_PERFCTR_INST_INT_LD = 0x95, + A11_PMU_PERFCTR_INST_INT_ST = 0x96, + A11_PMU_PERFCTR_INST_INT_ALU = 0x97, + A11_PMU_PERFCTR_INST_SIMD_LD = 0x98, + A11_PMU_PERFCTR_INST_SIMD_ST = 0x99, + A11_PMU_PERFCTR_INST_SIMD_ALU = 0x9a, + A11_PMU_PERFCTR_INST_LDST = 0x9b, + A11_PMU_PERFCTR_INST_BARRIER = 0x9c, + A11_PMU_PERFCTR_UNKNOWN_9f = 0x9f, + A11_PMU_PERFCTR_L1D_TLB_ACCESS = 0xa0, + A11_PMU_PERFCTR_L1D_TLB_MISS = 0xa1, + A11_PMU_PERFCTR_L1D_CACHE_MISS_ST = 0xa2, + A11_PMU_PERFCTR_L1D_CACHE_MISS_LD = 0xa3, + A11_PMU_PERFCTR_LD_UNIT_UOP = 0xa6, + A11_PMU_PERFCTR_ST_UNIT_UOP = 0xa7, + A11_PMU_PERFCTR_L1D_CACHE_WRITEBACK = 0xa8, + A11_PMU_PERFCTR_LDST_X64_UOP = 0xb1, + A11_PMU_PERFCTR_ATOMIC_OR_EXCLUSIVE_SUCC = 0xb3, + A11_PMU_PERFCTR_ATOMIC_OR_EXCLUSIVE_FAIL = 0xb4, + A11_PMU_PERFCTR_L1D_CACHE_MISS_LD_NONSPEC = 0xbf, + A11_PMU_PERFCTR_L1D_CACHE_MISS_ST_NONSPEC = 0xc0, + A11_PMU_PERFCTR_L1D_TLB_MISS_NONSPEC = 0xc1, + A11_PMU_PERFCTR_ST_MEMORY_ORDER_VIOLATION_NONSPEC = 0xc4, + A11_PMU_PERFCTR_BRANCH_COND_MISPRED_NONSPEC = 0xc5, + A11_PMU_PERFCTR_BRANCH_INDIR_MISPRED_NONSPEC = 0xc6, + A11_PMU_PERFCTR_BRANCH_RET_INDIR_MISPRED_NONSPEC = 0xc8, + A11_PMU_PERFCTR_BRANCH_CALL_INDIR_MISPRED_NONSPEC = 0xca, + A11_PMU_PERFCTR_BRANCH_MISPRED_NONSPEC = 0xcb, + A11_PMU_PERFCTR_FED_IC_MISS_DEMAND = 0xd3, + A11_PMU_PERFCTR_L1I_TLB_MISS_DEMAND = 0xd4, + A11_PMU_PERFCTR_MAP_DISPATCH_BUBBLE = 0xd6, + A11_PMU_PERFCTR_L1I_CACHE_MISS_DEMAND = 0xdb, + A11_PMU_PERFCTR_FETCH_RESTART = 0xde, + A11_PMU_PERFCTR_ST_NT_UOP = 0xe5, + A11_PMU_PERFCTR_LD_NT_UOP = 0xe6, + A11_PMU_PERFCTR_UNKNOWN_f5 = 0xf5, + A11_PMU_PERFCTR_UNKNOWN_f6 = 0xf6, + A11_PMU_PERFCTR_UNKNOWN_f7 = 0xf7, + A11_PMU_PERFCTR_UNKNOWN_f8 = 0xf8, + A11_PMU_PERFCTR_UNKNOWN_fd = 0xfd, + A11_PMU_PERFCTR_LAST = M1_PMU_CFG_EVENT, + + /* + * From this point onwards, these are not actual HW events, + * but attributes that get stored in hw->config_base. + */ + A11_PMU_CFG_COUNT_USER = BIT(8), + A11_PMU_CFG_COUNT_KERNEL = BIT(9), +}; + +static const u16 a11_pmu_event_affinity[A11_PMU_PERFCTR_LAST + 1] = { + [0 ... A11_PMU_PERFCTR_LAST] = ANY_BUT_0_1, + [A11_PMU_PERFCTR_RETIRE_UOP] = BIT(7), + [A11_PMU_PERFCTR_CORE_ACTIVE_CYCLE] = ANY_BUT_0_1 | BIT(0), + [A11_PMU_PERFCTR_INST_ALL] = BIT(7) | BIT(1), + [A11_PMU_PERFCTR_INST_BRANCH] = ONLY_5_6_7, + [A11_PMU_PERFCTR_INST_BRANCH_CALL] = ONLY_5_6_7, + [A11_PMU_PERFCTR_INST_BRANCH_RET] = ONLY_5_6_7, + [A11_PMU_PERFCTR_INST_BRANCH_TAKEN] = ONLY_5_6_7, + [A11_PMU_PERFCTR_INST_BRANCH_INDIR] = ONLY_5_6_7, + [A11_PMU_PERFCTR_INST_BRANCH_COND] = ONLY_5_6_7, + [A11_PMU_PERFCTR_INST_INT_LD] = ONLY_5_6_7, + [A11_PMU_PERFCTR_INST_INT_ST] = ONLY_5_6_7, + [A11_PMU_PERFCTR_INST_INT_ALU] = BIT(7), + [A11_PMU_PERFCTR_INST_SIMD_LD] = ONLY_5_6_7, + [A11_PMU_PERFCTR_INST_SIMD_ST] = ONLY_5_6_7, + [A11_PMU_PERFCTR_INST_SIMD_ALU] = BIT(7), + [A11_PMU_PERFCTR_INST_LDST] = ONLY_5_6_7, + [A11_PMU_PERFCTR_INST_BARRIER] = ONLY_5_6_7, + [A11_PMU_PERFCTR_UNKNOWN_9f] = BIT(7), + [A11_PMU_PERFCTR_L1D_CACHE_MISS_LD_NONSPEC] = ONLY_5_6_7, + [A11_PMU_PERFCTR_L1D_CACHE_MISS_ST_NONSPEC] = ONLY_5_6_7, + [A11_PMU_PERFCTR_L1D_TLB_MISS_NONSPEC] = ONLY_5_6_7, + [A11_PMU_PERFCTR_ST_MEMORY_ORDER_VIOLATION_NONSPEC] = ONLY_5_6_7, + [A11_PMU_PERFCTR_BRANCH_COND_MISPRED_NONSPEC] = ONLY_5_6_7, + [A11_PMU_PERFCTR_BRANCH_INDIR_MISPRED_NONSPEC] = ONLY_5_6_7, + [A11_PMU_PERFCTR_BRANCH_RET_INDIR_MISPRED_NONSPEC] = ONLY_5_6_7, + [A11_PMU_PERFCTR_BRANCH_CALL_INDIR_MISPRED_NONSPEC] = ONLY_5_6_7, + [A11_PMU_PERFCTR_BRANCH_MISPRED_NONSPEC] = ONLY_5_6_7, + [A11_PMU_PERFCTR_UNKNOWN_f5] = ONLY_2_4_6, + [A11_PMU_PERFCTR_UNKNOWN_f6] = ONLY_2_4_6, + [A11_PMU_PERFCTR_UNKNOWN_f7] = ONLY_2_4_6, + [A11_PMU_PERFCTR_UNKNOWN_f8] = ONLY_2_TO_7, + [A11_PMU_PERFCTR_UNKNOWN_fd] = ONLY_2_4_6, +}; + enum m1_pmu_events { M1_PMU_PERFCTR_RETIRE_UOP = 0x1, M1_PMU_PERFCTR_CORE_ACTIVE_CYCLE = 0x2, @@ -979,6 +1086,12 @@ static int a10_pmu_get_event_idx(struct pmu_hw_events *cpuc, return apple_pmu_get_event_idx(cpuc, event, a10_pmu_event_affinity); } +static int a11_pmu_get_event_idx(struct pmu_hw_events *cpuc, + struct perf_event *event) +{ + return apple_pmu_get_event_idx(cpuc, event, a11_pmu_event_affinity); +} + static int m1_pmu_get_event_idx(struct pmu_hw_events *cpuc, struct perf_event *event) { @@ -1158,6 +1271,26 @@ static int a10_pmu_fusion_init(struct arm_pmu *cpu_pmu) return apple_pmu_init_common(cpu_pmu, ARMPMU_EVT_47BIT, M1_PMU_NR_COUNTERS); } +static int a11_pmu_monsoon_init(struct arm_pmu *cpu_pmu) +{ + cpu_pmu->name = "apple_monsoon_pmu"; + cpu_pmu->get_event_idx = a11_pmu_get_event_idx; + cpu_pmu->map_event = m1_pmu_map_event; + cpu_pmu->reset = m1_pmu_reset; + cpu_pmu->start = m1_pmu_start; + return apple_pmu_init_common(cpu_pmu, ARMPMU_EVT_47BIT, M1_PMU_NR_COUNTERS); +} + +static int a11_pmu_mistral_init(struct arm_pmu *cpu_pmu) +{ + cpu_pmu->name = "apple_mistral_pmu"; + cpu_pmu->get_event_idx = a11_pmu_get_event_idx; + cpu_pmu->map_event = m1_pmu_map_event; + cpu_pmu->reset = m1_pmu_reset; + cpu_pmu->start = m1_pmu_start; + return apple_pmu_init_common(cpu_pmu, ARMPMU_EVT_47BIT, M1_PMU_NR_COUNTERS); +} + static int m1_pmu_ice_init(struct arm_pmu *cpu_pmu) { cpu_pmu->name = "apple_icestorm_pmu"; @@ -1204,6 +1337,8 @@ static const struct of_device_id m1_pmu_of_device_ids[] = { { .compatible = "apple,icestorm-pmu", .data = m1_pmu_ice_init, }, { .compatible = "apple,firestorm-pmu", .data = m1_pmu_fire_init, }, { .compatible = "apple,fusion-pmu", .data = a10_pmu_fusion_init, }, + { .compatible = "apple,monsoon-pmu", .data = a11_pmu_monsoon_init, }, + { .compatible = "apple,mistral-pmu", .data = a11_pmu_mistral_init, }, { .compatible = "apple,twister-pmu", .data = a9_pmu_twister_init, }, { .compatible = "apple,typhoon-pmu", .data = a8_pmu_typhoon_init, }, { .compatible = "apple,cyclone-pmu", .data = a7_pmu_cyclone_init, },