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Fri, 21 Feb 2025 07:41:21 GMT Received: from yuanfang4-gv.ap.qualcomm.com (10.80.80.8) by nalasex01b.na.qualcomm.com (10.47.209.197) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Thu, 20 Feb 2025 23:41:15 -0800 From: Yuanfang Zhang Date: Fri, 21 Feb 2025 15:40:32 +0800 Subject: [PATCH 5/5] coresight-tnoc: add nodes to configure freq packet MIME-Version: 1.0 Message-ID: <20250221-trace-noc-driver-v1-5-0a23fc643217@quicinc.com> References: <20250221-trace-noc-driver-v1-0-0a23fc643217@quicinc.com> In-Reply-To: <20250221-trace-noc-driver-v1-0-0a23fc643217@quicinc.com> To: Suzuki K Poulose , Mike Leach , James Clark , "Alexander Shishkin" , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: , , , , , , , Yuanfang Zhang X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1740123657; l=3505; i=quic_yuanfang@quicinc.com; s=20241209; h=from:subject:message-id; bh=D9nO0Rw8IFdx8/JC61W3qCybMF46rPTusGdMNvOiv98=; b=Pg9D/It6JCg3UbWpboZ7/yl03luOty/kj91bts+ObZgzhD0bK+AkH3++9Ddqc8nOGpOTErFwC Yp6bgMtxsTyA37r6nllO0l4TbHjYOxxMFxOMj4QXdOQomIUv6xLqla5 X-Developer-Key: i=quic_yuanfang@quicinc.com; a=ed25519; pk=ZrIjRVq9LN8/zCQGbDEwrZK/sfnVjwQ2elyEZAOaV1Q= X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01b.na.qualcomm.com (10.47.209.197) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: oPYiKrnMqhSUHPyHOZ4HPQlBRtihjGZN X-Proofpoint-GUID: oPYiKrnMqhSUHPyHOZ4HPQlBRtihjGZN X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1057,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-02-21_01,2025-02-20_02,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 clxscore=1015 bulkscore=0 phishscore=0 mlxlogscore=999 suspectscore=0 priorityscore=1501 mlxscore=0 spamscore=0 adultscore=0 malwarescore=0 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2502100000 definitions=main-2502210056 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250220_234128_001852_D5CBFDAD X-CRM114-Status: GOOD ( 14.86 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Three nodes for freq packet config are added here: 1. freq_type: used to set the type of issued ATB FREQ packets. 0: 'FREQ' packets; 1: 'FREQ_TS' packets. 2. freq_req_val: used to set frequency values carried by 'FREQ' and 'FREQ_TS' packets. 3. freq_ts_req: writing '1' to issue a 'FREQ' or 'FREQ_TS' packet. Signed-off-by: Yuanfang Zhang --- drivers/hwtracing/coresight/coresight-tnoc.c | 97 ++++++++++++++++++++++++++++ 1 file changed, 97 insertions(+) diff --git a/drivers/hwtracing/coresight/coresight-tnoc.c b/drivers/hwtracing/coresight/coresight-tnoc.c index 3ff3504603f66bd595484374f1cdac90c528b665..629df98959d1bfb55771376fac2818a48cb9c259 100644 --- a/drivers/hwtracing/coresight/coresight-tnoc.c +++ b/drivers/hwtracing/coresight/coresight-tnoc.c @@ -112,10 +112,107 @@ static ssize_t flag_type_show(struct device *dev, } static DEVICE_ATTR_RW(flag_type); +static ssize_t freq_type_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct trace_noc_drvdata *drvdata = dev_get_drvdata(dev->parent); + + return sysfs_emit(buf, "%u\n", drvdata->freq_type); +} + +static ssize_t freq_type_store(struct device *dev, + struct device_attribute *attr, + const char *buf, + size_t size) +{ + struct trace_noc_drvdata *drvdata = dev_get_drvdata(dev->parent); + unsigned long val; + + if (kstrtoul(buf, 0, &val)) + return -EINVAL; + + if (val != 1 && val != 0) + return -EINVAL; + + spin_lock(&drvdata->spinlock); + if (val) + drvdata->freq_type = FREQ_TS; + else + drvdata->freq_type = FREQ; + spin_unlock(&drvdata->spinlock); + + return size; +} +static DEVICE_ATTR_RW(freq_type); + +static ssize_t freq_req_val_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct trace_noc_drvdata *drvdata = dev_get_drvdata(dev->parent); + + return sysfs_emit(buf, "%u\n", drvdata->freq_req_val); +} + +static ssize_t freq_req_val_store(struct device *dev, + struct device_attribute *attr, + const char *buf, + size_t size) +{ + struct trace_noc_drvdata *drvdata = dev_get_drvdata(dev->parent); + unsigned long val; + + if (kstrtoul(buf, 0, &val)) + return -EINVAL; + + if (val) { + spin_lock(&drvdata->spinlock); + drvdata->freq_req_val = val; + spin_unlock(&drvdata->spinlock); + } + + return size; +} +static DEVICE_ATTR_RW(freq_req_val); + +static ssize_t freq_ts_req_store(struct device *dev, + struct device_attribute *attr, + const char *buf, + size_t size) +{ + struct trace_noc_drvdata *drvdata = dev_get_drvdata(dev->parent); + struct coresight_device *csdev = drvdata->csdev; + unsigned long val; + u32 reg; + + if (kstrtoul(buf, 0, &val)) + return -EINVAL; + + spin_lock(&drvdata->spinlock); + if (csdev->refcnt == 0) { + spin_unlock(&drvdata->spinlock); + return -EPERM; + } + + if (val) { + reg = readl_relaxed(drvdata->base + TRACE_NOC_CTRL); + reg = reg | TRACE_NOC_CTRL_FREQTSREQ; + writel_relaxed(reg, drvdata->base + TRACE_NOC_CTRL); + } + spin_unlock(&drvdata->spinlock); + + return size; +} +static DEVICE_ATTR_WO(freq_ts_req); + static struct attribute *trace_noc_attrs[] = { &dev_attr_flush_req.attr, &dev_attr_flush_status.attr, &dev_attr_flag_type.attr, + &dev_attr_freq_type.attr, + &dev_attr_freq_req_val.attr, + &dev_attr_freq_ts_req.attr, NULL, };