From patchwork Mon Feb 24 09:55:04 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ryan Chen X-Patchwork-Id: 13987752 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 5D71BC021A4 for ; Mon, 24 Feb 2025 10:04:44 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Type: Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date :Subject:To:From:Reply-To:Cc:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=DUeLil7NYb5vFj2LmQhnckZiCgj3SfnkLx7lSucrD3s=; b=NqICHWxobcUVUk1QetKugpTiQa WbE+/T/2nuVgk68ujMtkHdTYz7aCMVUup/RgmRP9H/k1VfYPJOrFfAWJxgwShMDdPhe3wg06kq4ia ezsH6cGWtolGd8Q4xpgXwr1aOFqkNnNvNDsrq134RnxPjCkQNfSEIPrJyu+FezQlXIM0M2rr+YspJ gpQU6rvwHrxZitnG3gDPkzky7G7ySMRJBJlZoOhnY/nQJMMGV33wdQpa3Q9V75MfaGLRjlWeu8zwp 5omnudMd676D74aCEccx36u6xvnjibxBwnoNPBr6JPnM1pPuRnYyfk0uLAWMkr56WueVeZB0M4pmK v5zeCpUA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1tmVK8-0000000D2ac-2yLj; Mon, 24 Feb 2025 10:04:28 +0000 Received: from mail.aspeedtech.com ([211.20.114.72] helo=TWMBX01.aspeed.com) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1tmVBD-0000000D00N-2oHa for linux-arm-kernel@lists.infradead.org; Mon, 24 Feb 2025 09:55:16 +0000 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.12; Mon, 24 Feb 2025 17:55:07 +0800 Received: from twmbx02.aspeed.com (192.168.10.13) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1258.12 via Frontend Transport; Mon, 24 Feb 2025 17:55:07 +0800 From: Ryan Chen To: ryan_chen , Michael Turquette , Stephen Boyd , Philipp Zabel , Joel Stanley , Andrew Jeffery , Rob Herring , Krzysztof Kozlowski , Conor Dooley , , , , , Subject: [PATCH v9 1/3] dt-binding: clock: ast2700: modify soc0/1 clock define Date: Mon, 24 Feb 2025 17:55:04 +0800 Message-ID: <20250224095506.2047064-2-ryan_chen@aspeedtech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250224095506.2047064-1-ryan_chen@aspeedtech.com> References: <20250224095506.2047064-1-ryan_chen@aspeedtech.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250224_015515_707768_3C30837F X-CRM114-Status: UNSURE ( 9.26 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org -remove redundant SOC0_CLK_UART_DIV13: SOC0_CLK_UART_DIV13 is not use at clk-ast2700.c, the clock source tree is uart clk src -> uart_div_table -> uart clk. -Change SOC0_CLK_HPLL_DIV_AHB to SOC0_CLK_AHBMUX: modify clock tree implement. older CLK_AHB use mpll_div_ahb/hpll_div_ahb to be ahb clock source. mpll->mpll_div_ahb -> clk_ahb hpll->hpll_div_ahb new use SOC0_CLK_AHBMUX for more understand clock source divide tree. mpll-> ahb_mux -> div_table -> clk_ahb hpll-> -new add clock: SOC0_CLK_MPHYSRC: UFS MPHY clock source. SOC0_CLK_U2PHY_REFCLKSRC: USB2.0 phy clock reference source. SOC1_CLK_I3C: I3C clock source. Signed-off-by: Ryan Chen --- include/dt-bindings/clock/aspeed,ast2700-scu.h | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/include/dt-bindings/clock/aspeed,ast2700-scu.h b/include/dt-bindings/clock/aspeed,ast2700-scu.h index 63021af3caf5..c7389530629d 100644 --- a/include/dt-bindings/clock/aspeed,ast2700-scu.h +++ b/include/dt-bindings/clock/aspeed,ast2700-scu.h @@ -13,18 +13,17 @@ #define SCU0_CLK_24M 1 #define SCU0_CLK_192M 2 #define SCU0_CLK_UART 3 -#define SCU0_CLK_UART_DIV13 3 #define SCU0_CLK_PSP 4 #define SCU0_CLK_HPLL 5 #define SCU0_CLK_HPLL_DIV2 6 #define SCU0_CLK_HPLL_DIV4 7 -#define SCU0_CLK_HPLL_DIV_AHB 8 +#define SCU0_CLK_AHBMUX 8 #define SCU0_CLK_DPLL 9 #define SCU0_CLK_MPLL 10 #define SCU0_CLK_MPLL_DIV2 11 #define SCU0_CLK_MPLL_DIV4 12 #define SCU0_CLK_MPLL_DIV8 13 -#define SCU0_CLK_MPLL_DIV_AHB 14 +#define SCU0_CLK_MPHYSRC 14 #define SCU0_CLK_D0 15 #define SCU0_CLK_D1 16 #define SCU0_CLK_CRT0 17 @@ -68,6 +67,7 @@ #define SCU0_CLK_GATE_UFSCLK 53 #define SCU0_CLK_GATE_EMMCCLK 54 #define SCU0_CLK_GATE_RVAS1CLK 55 +#define SCU0_CLK_U2PHY_REFCLKSRC 56 /* SOC1 clk */ #define SCU1_CLKIN 0 @@ -160,4 +160,5 @@ #define SCU1_CLK_GATE_PORTDUSB2CLK 85 #define SCU1_CLK_GATE_LTPI1TXCLK 86 +#define SCU1_CLK_I3C 87 #endif