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Wed, 26 Feb 2025 11:06:23 GMT Received: from yuanfang4-gv.ap.qualcomm.com (10.80.80.8) by nalasex01b.na.qualcomm.com (10.47.209.197) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 26 Feb 2025 03:06:16 -0800 From: Yuanfang Zhang Date: Wed, 26 Feb 2025 19:05:50 +0800 Subject: [PATCH v2 1/5] dt-bindings: arm: Add Coresight device Trace NOC definition MIME-Version: 1.0 Message-ID: <20250226-trace-noc-driver-v2-1-8afc6584afc5@quicinc.com> References: <20250226-trace-noc-driver-v2-0-8afc6584afc5@quicinc.com> In-Reply-To: <20250226-trace-noc-driver-v2-0-8afc6584afc5@quicinc.com> To: Suzuki K Poulose , Mike Leach , James Clark , "Alexander Shishkin" , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: , , , , , , , Yuanfang Zhang X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1740567972; l=3550; i=quic_yuanfang@quicinc.com; s=20241209; h=from:subject:message-id; bh=mQRaiDx0oUaGa2qOav58eJ/XL1EVd3She1ceBivGTsg=; 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Signed-off-by: Yuanfang Zhang --- .../bindings/arm/qcom,coresight-tnoc.yaml | 116 +++++++++++++++++++++ 1 file changed, 116 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/qcom,coresight-tnoc.yaml b/Documentation/devicetree/bindings/arm/qcom,coresight-tnoc.yaml new file mode 100644 index 0000000000000000000000000000000000000000..2d806cc34c381d27b47dcce126ce5bcf468826a8 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/qcom,coresight-tnoc.yaml @@ -0,0 +1,116 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/qcom,coresight-tnoc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Ttrace NOC(Network On Chip) + +maintainers: + - yuanfang Zhang + +description: + The Trace NoC is an integration hierarchy which is a replacement of Dragonlink + tile configuration. It brings together debug component like TPDA, funnel and + interconnect Trace Noc which collects trace from subsystems and transfers to + QDSS sink. + + It sits in the different subsystem of SOC and aggregates the trace and + transports it to Aggregation TNoC or to QDSS trace sink eventually. Trace NoC + embeds bridges for all the interfaces(APB, ATB, QPMDA & NTS). + + Trace NoC can take inputs from different trace sources i.e. ATB, QPMDA. + +# Need a custom select here or 'arm,primecell' will match on lots of nodes +select: + properties: + compatible: + contains: + enum: + - qcom,coresight-tnoc + required: + - compatible + +properties: + $nodename: + pattern: "^tn(@[0-9a-f]+)$" + + compatible: + items: + - const: qcom,coresight-tnoc + - const: arm,primecell + + reg: + minItems: 1 + maxItems: 2 + description: + Physical address space of the device. + + clocks: + maxItems: 1 + description: + Clock sources used by the device. + + clock-names: + items: + - const: apb_pclk + + in-ports: + $ref: /schemas/graph.yaml#/properties/ports + + patternProperties: + '^port(@[0-9a-f]+)?$': + description: Input connections from CoreSight Trace bus + $ref: /schemas/graph.yaml#/properties/port + + out-ports: + $ref: /schemas/graph.yaml#/properties/ports + additionalProperties: false + + properties: + port: + description: + Output connection to CoreSight Trace bus + $ref: /schemas/graph.yaml#/properties/port + +required: + - compatible + - reg + - clocks + - clock-names + - in-ports + - out-ports + +additionalProperties: false + +examples: + - | + tn@109ab000 { + compatible = "qcom,coresight-tnoc", "arm,primecell"; + reg = <0x0 0x109ab000 0x0 0x4200>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + tn_ag_in_tpdm_gcc: endpoint { + remote-endpoint = <&tpdm_gcc_out_tn_ag>; + }; + }; + }; + + out-ports { + port { + tn_ag_out_funnel_in1: endpoint { + remote-endpoint = <&funnel_in1_in_tn_ag>; + }; + }; + }; + }; +...