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Wed, 26 Feb 2025 06:40:27 GMT Received: from hu-jinlmao-lv.qualcomm.com (10.49.16.6) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Tue, 25 Feb 2025 22:40:26 -0800 From: Mao Jinlong To: Suzuki K Poulose , Mike Leach , James Clark , "Alexander Shishkin" CC: Tao Zhang , , , , , Mao Jinlong Subject: [PATCH v4 2/3] coresight-tpdm: Add support to select lane Date: Tue, 25 Feb 2025 22:40:07 -0800 Message-ID: <20250226064008.2531037-3-quic_jinlmao@quicinc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250226064008.2531037-1-quic_jinlmao@quicinc.com> References: <20250226064008.2531037-1-quic_jinlmao@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.49.16.6] X-ClientProxiedBy: nalasex01c.na.qualcomm.com (10.47.97.35) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: jqImbic_HHBnwl0g2xY8MqtxfPFCZyDh X-Proofpoint-ORIG-GUID: jqImbic_HHBnwl0g2xY8MqtxfPFCZyDh X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1057,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-02-25_08,2025-02-26_01,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 mlxscore=0 bulkscore=0 lowpriorityscore=0 phishscore=0 clxscore=1015 malwarescore=0 impostorscore=0 adultscore=0 priorityscore=1501 spamscore=0 mlxlogscore=999 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2502100000 definitions=main-2502260051 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250225_224034_952595_CBD754FA X-CRM114-Status: GOOD ( 16.76 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Tao Zhang TPDM MCMB subunits supports up to 8 lanes CMB. For MCMB configurations, the field "XTRIG_LNSEL" in CMB_CR register selects which lane participates in the output pattern mach cross trigger mechanism governed by the M_CMB_DXPR and M_CMB_XPMR regisers. Signed-off-by: Tao Zhang Signed-off-by: Mao Jinlong --- .../testing/sysfs-bus-coresight-devices-tpdm | 8 +++ drivers/hwtracing/coresight/coresight-tpdm.c | 51 +++++++++++++++++++ drivers/hwtracing/coresight/coresight-tpdm.h | 3 ++ 3 files changed, 62 insertions(+) diff --git a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm index bf710ea6e0ef..547540e330c6 100644 --- a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm +++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm @@ -257,3 +257,11 @@ Contact: Jinlong Mao (QUIC) , Tao Zhang (QUIC) /mcmb_trig_lane +Date: Feb 2025 +KernelVersion 6.15 +Contact: Jinlong Mao (QUIC) , Tao Zhang (QUIC) +Description: + (RW) Set/Get which lane participates in the output pattern + match cross trigger mechanism for the MCMB subunit TPDM. diff --git a/drivers/hwtracing/coresight/coresight-tpdm.c b/drivers/hwtracing/coresight/coresight-tpdm.c index 9ec4322cd73a..c57f8da2962e 100644 --- a/drivers/hwtracing/coresight/coresight-tpdm.c +++ b/drivers/hwtracing/coresight/coresight-tpdm.c @@ -252,6 +252,18 @@ static umode_t tpdm_cmb_msr_is_visible(struct kobject *kobj, return 0; } +static umode_t tpdm_mcmb_is_visible(struct kobject *kobj, + struct attribute *attr, int n) +{ + struct device *dev = kobj_to_dev(kobj); + struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent); + + if (drvdata && tpdm_has_mcmb_dataset(drvdata)) + return attr->mode; + + return 0; +} + static void tpdm_reset_datasets(struct tpdm_drvdata *drvdata) { if (tpdm_has_dsb_dataset(drvdata)) { @@ -1020,6 +1032,34 @@ static ssize_t cmb_trig_ts_store(struct device *dev, } static DEVICE_ATTR_RW(cmb_trig_ts); +static ssize_t mcmb_trig_lane_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent); + + return sysfs_emit(buf, "%u\n", + (unsigned int)drvdata->cmb->mcmb.trig_lane); +} + +static ssize_t mcmb_trig_lane_store(struct device *dev, + struct device_attribute *attr, + const char *buf, + size_t size) +{ + struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent); + unsigned long val; + + if ((kstrtoul(buf, 0, &val)) || (val >= TPDM_MCMB_MAX_LANES)) + return -EINVAL; + + guard(spinlock)(&drvdata->spinlock); + drvdata->cmb->mcmb.trig_lane = val; + + return size; +} +static DEVICE_ATTR_RW(mcmb_trig_lane); + static struct attribute *tpdm_dsb_edge_attrs[] = { &dev_attr_ctrl_idx.attr, &dev_attr_ctrl_val.attr, @@ -1182,6 +1222,11 @@ static struct attribute *tpdm_cmb_msr_attrs[] = { NULL, }; +static struct attribute *tpdm_mcmb_attrs[] = { + &dev_attr_mcmb_trig_lane.attr, + NULL, +}; + static struct attribute *tpdm_dsb_attrs[] = { &dev_attr_dsb_mode.attr, &dev_attr_dsb_trig_ts.attr, @@ -1248,6 +1293,11 @@ static struct attribute_group tpdm_cmb_msr_grp = { .name = "cmb_msr", }; +static struct attribute_group tpdm_mcmb_attr_grp = { + .attrs = tpdm_mcmb_attrs, + .is_visible = tpdm_mcmb_is_visible, +}; + static const struct attribute_group *tpdm_attr_grps[] = { &tpdm_attr_grp, &tpdm_dsb_attr_grp, @@ -1259,6 +1309,7 @@ static const struct attribute_group *tpdm_attr_grps[] = { &tpdm_cmb_trig_patt_grp, &tpdm_cmb_patt_grp, &tpdm_cmb_msr_grp, + &tpdm_mcmb_attr_grp, NULL, }; diff --git a/drivers/hwtracing/coresight/coresight-tpdm.h b/drivers/hwtracing/coresight/coresight-tpdm.h index 62a3fd5ddec7..932c5dfc89b1 100644 --- a/drivers/hwtracing/coresight/coresight-tpdm.h +++ b/drivers/hwtracing/coresight/coresight-tpdm.h @@ -45,6 +45,9 @@ /* MAX number of DSB MSR */ #define TPDM_CMB_MAX_MSR 32 +/* MAX lanes in the output pattern for MCMB configurations*/ +#define TPDM_MCMB_MAX_LANES 8 + /* DSB Subunit Registers */ #define TPDM_DSB_CR (0x780) #define TPDM_DSB_TIER (0x784)