diff mbox series

[2/2] clk: sunxi-ng: d1: Add missing divider for MMC mod clocks

Message ID 20250226103734.1252013-3-andre.przywara@arm.com (mailing list archive)
State New
Headers show
Series clk: sunxi-ng: d1: Fix halved MMC frequency | expand

Commit Message

Andre Przywara Feb. 26, 2025, 10:37 a.m. UTC 
The D1/R528/T113 SoCs have a hidden divider of 2 in the MMC mod clocks,
just as other recent SoCs. So far we did not describe that, which led
to the resulting MMC clock rate to be only half of its intended value.

Use a macro that allows to describe a fixed post-divider, to compensate
for that divisor.

This brings the MMC performance on those SoCs to its expected level,
so about 23 MB/s for SD cards, instead of the 11 MB/s measured so far.

Fixes: 35b97bb94111 ("clk: sunxi-ng: Add support for the D1 SoC clocks")
Reported-by: Kuba Szczodrzyński <kuba@szczodrzynski.pl>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
---
 drivers/clk/sunxi-ng/ccu-sun20i-d1.c | 43 ++++++++++++++++------------
 1 file changed, 25 insertions(+), 18 deletions(-)

Comments

Jernej Škrabec Feb. 26, 2025, 4:06 p.m. UTC | #1 
Dne sreda, 26. februar 2025 ob 11:37:34 Srednjeevropski standardni čas je Andre Przywara napisal(a):
> The D1/R528/T113 SoCs have a hidden divider of 2 in the MMC mod clocks,
> just as other recent SoCs. So far we did not describe that, which led
> to the resulting MMC clock rate to be only half of its intended value.
> 
> Use a macro that allows to describe a fixed post-divider, to compensate
> for that divisor.
> 
> This brings the MMC performance on those SoCs to its expected level,
> so about 23 MB/s for SD cards, instead of the 11 MB/s measured so far.
> 
> Fixes: 35b97bb94111 ("clk: sunxi-ng: Add support for the D1 SoC clocks")
> Reported-by: Kuba Szczodrzyński <kuba@szczodrzynski.pl>
> Signed-off-by: Andre Przywara <andre.przywara@arm.com>

Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>

Best regards,
Jernej
diff mbox series

Patch

diff --git a/drivers/clk/sunxi-ng/ccu-sun20i-d1.c b/drivers/clk/sunxi-ng/ccu-sun20i-d1.c
index bb66c906ebbb6..d52a0ef43ea6c 100644
--- a/drivers/clk/sunxi-ng/ccu-sun20i-d1.c
+++ b/drivers/clk/sunxi-ng/ccu-sun20i-d1.c
@@ -412,19 +412,24 @@  static const struct clk_parent_data mmc0_mmc1_parents[] = {
 	{ .hw = &pll_periph0_2x_clk.common.hw },
 	{ .hw = &pll_audio1_div2_clk.common.hw },
 };
-static SUNXI_CCU_MP_DATA_WITH_MUX_GATE(mmc0_clk, "mmc0", mmc0_mmc1_parents, 0x830,
-				       0, 4,	/* M */
-				       8, 2,	/* P */
-				       24, 3,	/* mux */
-				       BIT(31),	/* gate */
-				       0);
 
-static SUNXI_CCU_MP_DATA_WITH_MUX_GATE(mmc1_clk, "mmc1", mmc0_mmc1_parents, 0x834,
-				       0, 4,	/* M */
-				       8, 2,	/* P */
-				       24, 3,	/* mux */
-				       BIT(31),	/* gate */
-				       0);
+static SUNXI_CCU_MP_MUX_GATE_POSTDIV_FEAT(mmc0_clk, "mmc0", mmc0_mmc1_parents,
+					  0x830,
+					  0, 4,		/* M */
+					  8, 2,		/* P */
+					  24, 3,	/* mux */
+					  BIT(31),	/* gate */
+					  2,            /* post-div */
+					  0, 0);
+
+static SUNXI_CCU_MP_MUX_GATE_POSTDIV_FEAT(mmc1_clk, "mmc1", mmc0_mmc1_parents,
+					  0x834,
+					  0, 4,		/* M */
+					  8, 2,		/* P */
+					  24, 3,	/* mux */
+					  BIT(31),	/* gate */
+					  2,            /* post-div */
+					  0, 0);
 
 static const struct clk_parent_data mmc2_parents[] = {
 	{ .fw_name = "hosc" },
@@ -433,12 +438,14 @@  static const struct clk_parent_data mmc2_parents[] = {
 	{ .hw = &pll_periph0_800M_clk.common.hw },
 	{ .hw = &pll_audio1_div2_clk.common.hw },
 };
-static SUNXI_CCU_MP_DATA_WITH_MUX_GATE(mmc2_clk, "mmc2", mmc2_parents, 0x838,
-				       0, 4,	/* M */
-				       8, 2,	/* P */
-				       24, 3,	/* mux */
-				       BIT(31),	/* gate */
-				       0);
+static SUNXI_CCU_MP_MUX_GATE_POSTDIV_FEAT(mmc2_clk, "mmc2", mmc2_parents,
+					  0x838,
+					  0, 4,	/* M */
+					  8, 2,	/* P */
+					  24, 3,	/* mux */
+					  BIT(31),	/* gate */
+					  2,            /* post-div */
+					  0, 0);
 
 static SUNXI_CCU_GATE_HWS(bus_mmc0_clk, "bus-mmc0", psi_ahb_hws,
 			  0x84c, BIT(0), 0);