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Thu, 27 Feb 2025 20:12:18 -0800 (PST) From: Nick Chan Date: Fri, 28 Feb 2025 12:06:44 +0800 Subject: [PATCH v5 04/11] drivers/perf: apple_m1: Support configuring counters for 32-bit EL0 MIME-Version: 1.0 Message-Id: <20250228-apple-cpmu-v5-4-9e124cd28ed4@gmail.com> References: <20250228-apple-cpmu-v5-0-9e124cd28ed4@gmail.com> In-Reply-To: <20250228-apple-cpmu-v5-0-9e124cd28ed4@gmail.com> To: Will Deacon , Mark Rutland , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Catalin Marinas Cc: Marc Zyngier , linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org, devicetree@vger.kernel.org, asahi@lists.linux.dev, linux-kernel@vger.kernel.org, Nick Chan X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=2104; i=towinchenmi@gmail.com; h=from:subject:message-id; bh=JtntoT+/7KJ8q2fmzw/EEFzk/pZROlC/KV344Upuyvg=; b=owEBbQKS/ZANAwAIAQHKCLemxQgkAcsmYgBnwTeI2VdJZOOjTGE9uIIIQVxJ8i1GHE0hgd69/ jSxub+VqWKJAjMEAAEIAB0WIQRLUnh4XJes95w8aIMBygi3psUIJAUCZ8E3iAAKCRABygi3psUI JKhsD/4/WmSMYbZ81VnJK3jgPs6enyxsl/w/5aDOv3Ne9UxU/40ChBvI3uieXq584y5AYzgd58p nz/L4FqUSQnWi+PC4lXn/kAENM+8nz8GsanCS1KiSBbfAfdjGJz9crz5LhFqgbwOLw/Txm/zQBn EvOIuSVo1pTEFRASfM46dpZ1j+YmGiCcsU4U6lwjUkEg4dr6h3Pf0D9iXlA5+FB0iLrzmIrRODX qI5pJUPnuarEf8eLXUa1Lrup+oxmy08SrY70DOZkGlr1qma0idQJ8JgLb9dD3mnRvVnKxGuSnhh 6JDUAenQXIMo5EtmFtLlNvVDVH0Jgk8xZcSzbgHYIMO9UUTv/KW9ju9+fR7eeYsmcAHzRozhBEM OOySpBt+OVu6XbNIjGfvJV/odKS4BuWTuLDiwvutUjpqhhluRPE70rmQepFNmOs1GY3JBrBmi9g wmXQy5IIfaY8okhNXAlDvncOgmzwkK760qhTRc9zH0Q/t3Zb4VVR9PMBOeo+vnvoLnfv3TrUQmo 0hQ57nUydTqyOq79T5v4FmwggG//1S16qtkxAGpHcG38X3OSh2g6x6wUY7e3sCEYKf9JNSdjfnI vYd5sJEt3ogAIIoQkOjsNujN8XNZow+rldB6wrwglmZPJxfNIaHn9cUL9yhQt/MShu3NA3QiUip SRpeluoRzf9LJmA== X-Developer-Key: i=towinchenmi@gmail.com; a=openpgp; fpr=4B5278785C97ACF79C3C688301CA08B7A6C50824 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250227_201219_635488_8C7D3F08 X-CRM114-Status: GOOD ( 11.84 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add support for configuring counters for 32-bit EL0 to allow adding support for implementations with 32-bit EL0. For documentation purposes, also add the bitmask for configuring counters for 64-bit EL3. Signed-off-by: Nick Chan --- arch/arm64/include/asm/apple_m1_pmu.h | 3 +++ drivers/perf/apple_m1_cpu_pmu.c | 6 ++++++ 2 files changed, 9 insertions(+) diff --git a/arch/arm64/include/asm/apple_m1_pmu.h b/arch/arm64/include/asm/apple_m1_pmu.h index 99483b19b99fca38483faad443ad4bcf4b85ef63..75be4b4c71f167a6874e22b38dc7c0bf30d25a47 100644 --- a/arch/arm64/include/asm/apple_m1_pmu.h +++ b/arch/arm64/include/asm/apple_m1_pmu.h @@ -37,8 +37,11 @@ #define PMCR0_PMI_ENABLE_8_9 GENMASK(45, 44) #define SYS_IMP_APL_PMCR1_EL1 sys_reg(3, 1, 15, 1, 0) +#define PMCR1_COUNT_A32_EL0_0_7 GENMASK(7, 0) #define PMCR1_COUNT_A64_EL0_0_7 GENMASK(15, 8) #define PMCR1_COUNT_A64_EL1_0_7 GENMASK(23, 16) +#define PMCR1_COUNT_A64_EL3_0_7 GENMASK(31, 24) +#define PMCR1_COUNT_A32_EL0_8_9 GENMASK(33, 32) #define PMCR1_COUNT_A64_EL0_8_9 GENMASK(41, 40) #define PMCR1_COUNT_A64_EL1_8_9 GENMASK(49, 48) diff --git a/drivers/perf/apple_m1_cpu_pmu.c b/drivers/perf/apple_m1_cpu_pmu.c index bf397fd81230007dcf52888f148e3158dc02e29d..73ba9861a15ff931b5e388b6d809dedb140e2292 100644 --- a/drivers/perf/apple_m1_cpu_pmu.c +++ b/drivers/perf/apple_m1_cpu_pmu.c @@ -335,10 +335,16 @@ static void m1_pmu_configure_counter(unsigned int index, u8 event, case 0 ... 7: user_bit = BIT(get_bit_offset(index, PMCR1_COUNT_A64_EL0_0_7)); kernel_bit = BIT(get_bit_offset(index, PMCR1_COUNT_A64_EL1_0_7)); + + if (system_supports_32bit_el0()) + user_bit |= BIT(get_bit_offset(index, PMCR1_COUNT_A32_EL0_0_7)); break; case 8 ... 9: user_bit = BIT(get_bit_offset(index - 8, PMCR1_COUNT_A64_EL0_8_9)); kernel_bit = BIT(get_bit_offset(index - 8, PMCR1_COUNT_A64_EL1_8_9)); + + if (system_supports_32bit_el0()) + user_bit |= BIT(get_bit_offset(index - 8, PMCR1_COUNT_A32_EL0_8_9)); break; default: BUG();