| Message ID | 20250228062246.24186-1-leilk.liu@mediatek.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | [v1] spi: mt65xx: add PM QoS support | expand |
Hi Leilk,
kernel test robot noticed the following build warnings:
[auto build test WARNING on broonie-spi/for-next]
[also build test WARNING on linus/master v6.14-rc4 next-20250228]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/Leilk-Liu/spi-mt65xx-add-PM-QoS-support/20250228-142359
base: https://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git for-next
patch link: https://lore.kernel.org/r/20250228062246.24186-1-leilk.liu%40mediatek.com
patch subject: [PATCH v1] spi: mt65xx: add PM QoS support
config: sh-randconfig-002-20250301 (https://download.01.org/0day-ci/archive/20250301/202503011637.9HYajsft-lkp@intel.com/config)
compiler: sh4-linux-gcc (GCC) 14.2.0
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20250301/202503011637.9HYajsft-lkp@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202503011637.9HYajsft-lkp@intel.com/
All warnings (new ones prefixed by >>):
>> drivers/spi/spi-mt65xx.c:177: warning: Function parameter or struct member 'qos_request' not described in 'mtk_spi'
vim +177 drivers/spi/spi-mt65xx.c
a568231f463225 Leilk Liu 2015-08-07 132
3c5cd2e23fe4c8 AngeloGioacchino Del Regno 2022-04-07 133 /**
3c5cd2e23fe4c8 AngeloGioacchino Del Regno 2022-04-07 134 * struct mtk_spi - SPI driver instance
3c5cd2e23fe4c8 AngeloGioacchino Del Regno 2022-04-07 135 * @base: Start address of the SPI controller registers
3c5cd2e23fe4c8 AngeloGioacchino Del Regno 2022-04-07 136 * @state: SPI controller state
3c5cd2e23fe4c8 AngeloGioacchino Del Regno 2022-04-07 137 * @pad_num: Number of pad_sel entries
3c5cd2e23fe4c8 AngeloGioacchino Del Regno 2022-04-07 138 * @pad_sel: Groups of pins to select
3c5cd2e23fe4c8 AngeloGioacchino Del Regno 2022-04-07 139 * @parent_clk: Parent of sel_clk
cae1578847e60a Yang Yingliang 2023-08-23 140 * @sel_clk: SPI host mux clock
3c5cd2e23fe4c8 AngeloGioacchino Del Regno 2022-04-07 141 * @spi_clk: Peripheral clock
3c5cd2e23fe4c8 AngeloGioacchino Del Regno 2022-04-07 142 * @spi_hclk: AHB bus clock
3c5cd2e23fe4c8 AngeloGioacchino Del Regno 2022-04-07 143 * @cur_transfer: Currently processed SPI transfer
3c5cd2e23fe4c8 AngeloGioacchino Del Regno 2022-04-07 144 * @xfer_len: Number of bytes to transfer
3c5cd2e23fe4c8 AngeloGioacchino Del Regno 2022-04-07 145 * @num_xfered: Number of transferred bytes
3c5cd2e23fe4c8 AngeloGioacchino Del Regno 2022-04-07 146 * @tx_sgl: TX transfer scatterlist
3c5cd2e23fe4c8 AngeloGioacchino Del Regno 2022-04-07 147 * @rx_sgl: RX transfer scatterlist
3c5cd2e23fe4c8 AngeloGioacchino Del Regno 2022-04-07 148 * @tx_sgl_len: Size of TX DMA transfer
3c5cd2e23fe4c8 AngeloGioacchino Del Regno 2022-04-07 149 * @rx_sgl_len: Size of RX DMA transfer
3c5cd2e23fe4c8 AngeloGioacchino Del Regno 2022-04-07 150 * @dev_comp: Device data structure
3c5cd2e23fe4c8 AngeloGioacchino Del Regno 2022-04-07 151 * @spi_clk_hz: Current SPI clock in Hz
3c5cd2e23fe4c8 AngeloGioacchino Del Regno 2022-04-07 152 * @spimem_done: SPI-MEM operation completion
3c5cd2e23fe4c8 AngeloGioacchino Del Regno 2022-04-07 153 * @use_spimem: Enables SPI-MEM
3c5cd2e23fe4c8 AngeloGioacchino Del Regno 2022-04-07 154 * @dev: Device pointer
3c5cd2e23fe4c8 AngeloGioacchino Del Regno 2022-04-07 155 * @tx_dma: DMA start for SPI-MEM TX
3c5cd2e23fe4c8 AngeloGioacchino Del Regno 2022-04-07 156 * @rx_dma: DMA start for SPI-MEM RX
3c5cd2e23fe4c8 AngeloGioacchino Del Regno 2022-04-07 157 */
a568231f463225 Leilk Liu 2015-08-07 158 struct mtk_spi {
a568231f463225 Leilk Liu 2015-08-07 159 void __iomem *base;
a568231f463225 Leilk Liu 2015-08-07 160 u32 state;
37457607ecaffe Leilk Liu 2015-10-26 161 int pad_num;
37457607ecaffe Leilk Liu 2015-10-26 162 u32 *pad_sel;
a740f4e684c020 Leilk Liu 2022-03-21 163 struct clk *parent_clk, *sel_clk, *spi_clk, *spi_hclk;
a568231f463225 Leilk Liu 2015-08-07 164 struct spi_transfer *cur_transfer;
a568231f463225 Leilk Liu 2015-08-07 165 u32 xfer_len;
00bca73bfca4fb Peter Shih 2018-09-10 166 u32 num_xfered;
a568231f463225 Leilk Liu 2015-08-07 167 struct scatterlist *tx_sgl, *rx_sgl;
a568231f463225 Leilk Liu 2015-08-07 168 u32 tx_sgl_len, rx_sgl_len;
a568231f463225 Leilk Liu 2015-08-07 169 const struct mtk_spi_compatible *dev_comp;
b0677bc0b5f41e Leilk Liu 2025-02-28 170 struct pm_qos_request qos_request;
162a31effc4182 Mason Zhang 2021-06-29 171 u32 spi_clk_hz;
9f763fd20da7d8 Leilk Liu 2022-03-21 172 struct completion spimem_done;
9f763fd20da7d8 Leilk Liu 2022-03-21 173 bool use_spimem;
9f763fd20da7d8 Leilk Liu 2022-03-21 174 struct device *dev;
9f763fd20da7d8 Leilk Liu 2022-03-21 175 dma_addr_t tx_dma;
9f763fd20da7d8 Leilk Liu 2022-03-21 176 dma_addr_t rx_dma;
a568231f463225 Leilk Liu 2015-08-07 @177 };
a568231f463225 Leilk Liu 2015-08-07 178
diff --git a/drivers/spi/spi-mt65xx.c b/drivers/spi/spi-mt65xx.c index 197bf2dbe5de..2ab65f858a21 100644 --- a/drivers/spi/spi-mt65xx.c +++ b/drivers/spi/spi-mt65xx.c @@ -20,6 +20,7 @@ #include <linux/spi/spi.h> #include <linux/spi/spi-mem.h> #include <linux/dma-mapping.h> +#include <linux/pm_qos.h> #define SPI_CFG0_REG 0x0000 #define SPI_CFG1_REG 0x0004 @@ -166,6 +167,7 @@ struct mtk_spi { struct scatterlist *tx_sgl, *rx_sgl; u32 tx_sgl_len, rx_sgl_len; const struct mtk_spi_compatible *dev_comp; + struct pm_qos_request qos_request; u32 spi_clk_hz; struct completion spimem_done; bool use_spimem; @@ -356,6 +358,7 @@ static int mtk_spi_hw_init(struct spi_controller *host, struct mtk_chip_config *chip_config = spi->controller_data; struct mtk_spi *mdata = spi_controller_get_devdata(host); + cpu_latency_qos_update_request(&mdata->qos_request, 500); cpha = spi->mode & SPI_CPHA ? 1 : 0; cpol = spi->mode & SPI_CPOL ? 1 : 0; @@ -459,6 +462,15 @@ static int mtk_spi_prepare_message(struct spi_controller *host, return mtk_spi_hw_init(host, msg->spi); } +static int mtk_spi_unprepare_message(struct spi_controller *host, + struct spi_message *message) +{ + struct mtk_spi *mdata = spi_controller_get_devdata(host); + + cpu_latency_qos_update_request(&mdata->qos_request, PM_QOS_DEFAULT_VALUE); + return 0; +} + static void mtk_spi_set_cs(struct spi_device *spi, bool enable) { u32 reg_val; @@ -1143,6 +1155,7 @@ static int mtk_spi_probe(struct platform_device *pdev) host->set_cs = mtk_spi_set_cs; host->prepare_message = mtk_spi_prepare_message; + host->unprepare_message = mtk_spi_unprepare_message; host->transfer_one = mtk_spi_transfer_one; host->can_dma = mtk_spi_can_dma; host->setup = mtk_spi_setup; @@ -1249,6 +1262,8 @@ static int mtk_spi_probe(struct platform_device *pdev) clk_disable_unprepare(mdata->spi_hclk); } + cpu_latency_qos_add_request(&mdata->qos_request, PM_QOS_DEFAULT_VALUE); + if (mdata->dev_comp->need_pad_sel) { if (mdata->pad_num != host->num_chipselect) return dev_err_probe(dev, -EINVAL, @@ -1292,6 +1307,7 @@ static void mtk_spi_remove(struct platform_device *pdev) struct mtk_spi *mdata = spi_controller_get_devdata(host); int ret; + cpu_latency_qos_remove_request(&mdata->qos_request); if (mdata->use_spimem && !completion_done(&mdata->spimem_done)) complete(&mdata->spimem_done);
Enable Quality of Service(QoS) support to speed up interrupt service routine handle. Sometimes, a gic interrupt will be generated after SPI transmission, but at this time the CPU is in an idle state and the processing handler will be ver slow. It takes time to exit the idle state and then become active. This will cause the SPI handler to execute slowly and cause SPI transfer timeouts. Signed-off-by: Leilk Liu <leilk.liu@mediatek.com> --- drivers/spi/spi-mt65xx.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+)