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Fri, 28 Feb 2025 11:18:32 +0100 From: Wadim Egorov To: , , , , , CC: , , , Subject: [PATCH 3/5] arm64: dts: ti: k3-am642-phyboard-electra: Add boot phase tags Date: Fri, 28 Feb 2025 11:18:15 +0100 Message-ID: <20250228101817.865811-3-w.egorov@phytec.de> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250228101817.865811-1-w.egorov@phytec.de> References: <20250228101817.865811-1-w.egorov@phytec.de> MIME-Version: 1.0 X-Originating-IP: [172.25.0.51] X-ClientProxiedBy: Diagnostix.phytec.de (172.25.0.14) To Florix.phytec.de (172.25.0.13) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: AMS0EPF000001A0:EE_|PR3P195MB0814:EE_ X-MS-Office365-Filtering-Correlation-Id: fabffd7f-c228-4691-a9ee-08dd57e14226 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|376014|1800799024|82310400026; X-Microsoft-Antispam-Message-Info: mcn3BHHji/ZOPbFgGgA+xAONwlIbItbJauPCnnAwiAG2RKVJhaDdr/ckOpbg5JSiZeYoPLvNznq6o6/6QMgb1ZnMAW5rEuqzEUSuj/UYE3BhwOi0ERK5TDEcoFwXENS9D6XOmZeCG94dbWYqQ0CX1jYERk1B31KvRv+J644Md3DrAJP4TZlfnefJDCbed7xRuFoEf6AUZajLUhexslmC+C9Ej0r9DWXXFy7IWa/qRUtTHJfXLsETNzSfGqkpj5+VWgQkI5GvoqB3FFGR0Q19PI4SXtJJjy0iSWKpgdaVDJnj426g0gFwHTnFEvsCFeep1l61PrvPjUTNRz0BaVL0F92UWkVr4JSAcxdlv15S6wPi0LsASe0611cRi/wo2AXYY9b/5XU93jWdstBGB8iPrx4fsaIq/HXuaex01OOFyDBlTsESMsSjxH71LsPhsHruQcwis4q0nWxvapHHiOsEt5hgyxavqoESM6/MYGXKPkbRGkO7mtGxdG11/5+c3kw979mdnofrRcCtbW4EjgcxOUku1SFhNFU0pzIlEVus+AOhWF8QBiofJJhVPaKeH46rPAMwW9t7iPm056k6knE6b4ap+aqeuZ0L5L5BhB4Cwpfa37H1OJiFa9VytrsR1D1Cx4WKjC9n6GM/z4o94F3/Vx96NFwHRfArkatmTd+tN9lrN4cByAgKhNclxMAwI4Z1MQW7UdKkXIXCKu6UIGv0Q2E+jgYenr1MdqIcX4GKLhNZdge2KSYoda6saaUuwKuY2HEgjUCnGb51nmV1tcWkGRvhhopNrkhoEUaaN97QLxP02u8xm/FSkZPZlVmJFXYNy1UvKq5vU2V2ZEevdBeQnQMYPTBWbsYD+nL5sowLoQMYstJgWpm/pv2JeI0NY2OJ1inLgbvqWOszhChrTIu8AZVlM3FSh63ttb9x9Lwy2o/txbbK7MMAnE0FXFWOgWu+v/z/v5YnFpmk99g9gV3DuPVBmXbOrfrNrxJmISizup5eP0SqIQEpgyZSDp4VlopvADdCZlT2+WvfxSMExLMilgTHJ+d5KcVPNZaKLLHXUB+i4fwT6a2R9bKDMad2iIgUV1aAZfWBj/+sK/BqAGXPkDgjlbZkthME7jGX6mUuR+YOFO2wxLa3dZd9ar+C9+W+RXUFPrMOZZGPg2pmUzU54fXBd41gveNzWuY8Oi7y7qnRGYPilezkIhrYcSYd11ztJuXzw8sN6Y0/QSikj1JWZhmENY47J88DS7no22ebRBAC+88uf/F1miO5KRVpnCwV5wwZ5BdVcltSYgXCeEta14bacsrspN3ErLh/ZZzbGRy93Juy5eiGut52wcIEkjKit3g1RhRRVrft6NiUtGwMN2gdhmF38HlnTr/UsCJlYfw2miB9fdkOGE9zLDiuJt/CdxgWFRsigfFohQmNBsIFhZ7qB5jOYhbNrquhLtTWOdneew1xhWZguBXY6tTrbycIDWFBYz6QY7zNBR1uH9sm1w== X-Forefront-Antispam-Report: CIP:91.26.50.189;CTRY:DE;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:Diagnostix.phytec.de;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(36860700013)(376014)(1800799024)(82310400026);DIR:OUT;SFP:1102; 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X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The bootph-all and bootph-pre-ram tags were introduced in dt-schema (dtschema/schemas/bootph.yaml) to define node usage across different boot phases. Add boot phase tags to all required nodes to ensure boot support from all sources, including UART, Ethernet, uSD card, eMMC, and OSPI NOR Flash. Signed-off-by: Wadim Egorov --- arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi | 12 ++++++++++++ .../boot/dts/ti/k3-am642-phyboard-electra-rdk.dts | 5 +++++ 2 files changed, 17 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi b/arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi index 99a6fdfaa7fb..52d53b690ac9 100644 --- a/arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi @@ -27,6 +27,7 @@ aliases { memory@80000000 { device_type = "memory"; reg = <0x00000000 0x80000000 0x00000000 0x80000000>; + bootph-all; }; reserved_memory: reserved-memory { @@ -132,6 +133,7 @@ AM64X_IOPAD(0x01f8, PIN_INPUT, 4) /* (P5) PRG0_PRU1_GPO18.MDIO0_MDIO */ AM64X_IOPAD(0x01fc, PIN_OUTPUT, 4) /* (R2) PRG0_PRU1_GPO19.MDIO0_MDC */ AM64X_IOPAD(0x0100, PIN_OUTPUT, 7) /* (V7) PRG1_PRU0_GPO18.GPIO0_63 */ >; + bootph-all; }; cpsw_rgmii1_pins_default: cpsw-rgmii1-default-pins { @@ -150,6 +152,7 @@ AM64X_IOPAD(0x01f4, PIN_INPUT, 4) /* (V5) PRG0_PRU1_GPO17.RGMII1_RD3 */ AM64X_IOPAD(0x014c, PIN_OUTPUT, 4) /* (AA14) PRG1_PRU1_GPO17.RGMII1_TD3 */ AM64X_IOPAD(0x0154, PIN_INPUT, 7) /* (V12) PRG1_PRU1_GPO19.GPIO0_84 */ >; + bootph-all; }; eeprom_wp_pins_default: eeprom-wp-default-pins { @@ -169,6 +172,7 @@ main_i2c0_pins_default: main-i2c0-default-pins { AM64X_IOPAD(0x0260, PIN_INPUT, 0) /* (A18) I2C0_SCL */ AM64X_IOPAD(0x0264, PIN_INPUT, 0) /* (B18) I2C0_SDA */ >; + bootph-all; }; ospi0_pins_default: ospi0-default-pins { @@ -185,6 +189,7 @@ AM64X_IOPAD(0x0024, PIN_INPUT, 0) /* (N18) OSPI0_D6 */ AM64X_IOPAD(0x0028, PIN_INPUT, 0) /* (M17) OSPI0_D7 */ AM64X_IOPAD(0x002c, PIN_OUTPUT, 0) /* (L19) OSPI0_CSn0 */ >; + bootph-all; }; rtc_pins_default: rtc-defaults-pins { @@ -197,6 +202,7 @@ AM64X_IOPAD(0x0278, PIN_INPUT, 7) /* (C19) EXTINTn.GPIO1_70 */ &cpsw3g { pinctrl-names = "default"; pinctrl-0 = <&cpsw_rgmii1_pins_default>; + bootph-all; status = "okay"; }; @@ -204,6 +210,7 @@ &cpsw3g_mdio { status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&cpsw_mdio_pins_default>; + bootph-all; cpsw3g_phy1: ethernet-phy@1 { compatible = "ethernet-phy-id2000.a231", "ethernet-phy-ieee802.3-c22"; @@ -215,12 +222,14 @@ cpsw3g_phy1: ethernet-phy@1 { reset-gpios = <&main_gpio0 63 GPIO_ACTIVE_LOW>; reset-assert-us = <1000>; reset-deassert-us = <1000>; + bootph-all; }; }; &cpsw_port1 { phy-mode = "rgmii-rxid"; phy-handle = <&cpsw3g_phy1>; + bootph-all; status = "okay"; }; @@ -266,6 +275,7 @@ &main_i2c0 { pinctrl-names = "default"; pinctrl-0 = <&main_i2c0_pins_default>; clock-frequency = <400000>; + bootph-all; eeprom@50 { compatible = "atmel,24c32"; @@ -377,6 +387,7 @@ serial_flash: flash@0 { cdns,tchsh-ns = <60>; cdns,tslch-ns = <60>; cdns,read-delay = <0>; + bootph-all; }; }; @@ -386,6 +397,7 @@ &sdhci0 { ti,driver-strength-ohm = <50>; disable-wp; keep-power-in-suspend; + bootph-all; }; &tscadc0 { diff --git a/arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-rdk.dts b/arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-rdk.dts index bc8e1ce11047..6fbd8d932396 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-rdk.dts +++ b/arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-rdk.dts @@ -171,6 +171,7 @@ vcc_3v3_mmc: regulator-sd { regulator-max-microvolt = <3300000>; regulator-boot-on; regulator-always-on; + bootph-all; }; }; @@ -275,6 +276,7 @@ AM64X_IOPAD(0x0290, PIN_INPUT, 0) /* MMC1_CLKLB */ AM64X_IOPAD(0x0294, PIN_INPUT_PULLUP, 0) /* (J19) MMC1_CMD */ AM64X_IOPAD(0x0298, PIN_INPUT_PULLUP, 0) /* (D19) MMC1_SDCD */ >; + bootph-all; }; main_spi0_pins_default: main-spi0-default-pins { @@ -291,6 +293,7 @@ main_uart0_pins_default: main-uart0-default-pins { AM64X_IOPAD(0x0230, PIN_INPUT, 0) /* (D15) UART0_RXD */ AM64X_IOPAD(0x0234, PIN_OUTPUT, 0) /* (C16) UART0_TXD */ >; + bootph-all; }; main_uart1_pins_default: main-uart1-default-pins { @@ -413,6 +416,7 @@ &main_uart0 { status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&main_uart0_pins_default>; + bootph-all; }; &main_uart1 { @@ -429,6 +433,7 @@ &sdhci1 { pinctrl-0 = <&main_mmc1_pins_default>; disable-wp; no-1-8-v; + bootph-all; }; &serdes0 {